form offset parameter to SYS; special register number */.

Arrangement for ARM64 SIMD instructions.

Arrangement for ARM64 SIMD instructions.

Arrangement for ARM64 SIMD instructions.

Arrangement for ARM64 SIMD instructions.

Arrangement for ARM64 SIMD instructions.

Arrangement for ARM64 SIMD instructions.

Arrangement for ARM64 SIMD instructions.

arrangement types.

Arrangement for ARM64 SIMD instructions.

Arrangement for ARM64 SIMD instructions.

Arrangement for ARM64 SIMD instructions.

Arrangement for ARM64 SIMD instructions.

Arrangement for ARM64 SIMD instructions.

branch instruction encodes 14 bits.

branch instruction encodes 19 bits.

ADDCON offset in auto constant $a(FP).

24-bit offset in auto constant $a(FP).

could be C_ADDCON or C_BITCON.

could be C_ADDCON0 or C_BITCON.

12-bit unsigned, shifted left by 0 or 12.

12-bit unsigned, unshifted.

24-bit constant.

TODO(aram): explain difference from C_VCONADDR.

ADDCON offset in extern constant $e(SB).

could be C_ADDCON or C_MOVCON.

Vn.<T>.

bitfield and logical immediate masks.

condition code, EQ, NE, etc.

Vn.<T>[index].

Rn.UXTB[<<3].

floating-point constant.

F0..F31.

The GOT slot for a symbol in -dynlink mode.

32-bit offset in auto constant $a(FP).

any other constant up to 64 bits.

any other constant up to 64 bits (needs pool literal).

32-bit constant.

[V1, V2, V3].

could be C_MOVCON or C_BITCON.

generated by a 16-bit constant, optionally inverted and/or shifted by multiple of 16.

a constant that can be loaded with one MOVZ/MOVN and one MOVK.

a constant that can be loaded with one MOVZ/MOVN and two MOVKs.

-4095 <= x < 0.

must be last.

starting from 1, leave unclassified Addr's class as 0.

-512 <= x < 0, 0 mod 8.

-512 <= x < 0, 0 mod 16.

-1024 <= x < 0, 0 mod 16.

-256 <= x < 0.

-256 <= x < 0, 0 mod 16.

-256 <= x < 0, 0 mod 4.

-256 <= x < 0, 0 mod 8.

must mirror C_NSAUTO_16, etc.

(Rn, Rm).

0 to 504, 0 mod 8.

0 to 504, 0 mod 16.

0 to 1008, 0 mod 16.

0 to 255.

0 to 255, 0 mod 16.

0 to 255, 0 mod 4.

0 to 255, 0 mod 8.

R0..R30.

register offset (including register extended).

R0..R30, RSP.

for TYPE_BRANCH.

0 to 4095, direct.

0 to 65520.

0 to 8190.

0 to 16380.

0 to 32760.

Rn<<2.

special operand, PLDL1KEEP, VMALLE1IS, etc.

REG_NZCV.

TLS "var" in initial exec mode: will become a memory address (chosen by the program linker) that the dynamic linker will fill with the offset from the thread local base.

TLS "var" in local exec mode: will become a constant offset from thread local base that is ultimately chosen by the program linker.

0 to 16380, 0 mod 4 + C_PSAUTO.

0 to 16380, 0 mod 16.

0 to 16380, 0 mod 8.

0 to 32760, 0 mod 8 + C_PSAUTO.

0 to 32760, 0 mod 16 + C_PSAUTO.

0 to 4095.

0 to 4095, 0 mod 16.

0 to 4095, 0 mod 2.

0 to 4095, 0 mod 4.

0 to 4095, 0 mod 8.

0 to 65520, 0 mod 16 + C_PSAUTO.

0 to 8190, 0 mod 2 + C_PSAUTO.

0 to 8190, 0 mod 16.

0 to 8190, 0 mod 4.

0 to 8190, 0 mod 8.

64-bit constant.

64-bit memory address.

V0..V31.

match arm.C_PBIT, so Prog.String know how to print it.

match arm.C_WBIT, so Prog.String know how to print it.

0(RSP).

$0.

0(R).

R0..R30, ZR.

first external register.

last register variable for 7g only.

first register variable.

Register assignments: compiler allocates R0 up as temps compiler allocates register variables R7-R25 compiler allocates external registers R26 down compiler allocates register variables F7-F26 compiler allocates external registers F26 down.

mark flags */.

p.From uses constant pool.

p.To uses constant pool.

number of floating point registers */.

p expands to multiple instructions, but does NOT use REGTMP.

number of general registers */.

Used for padding NOOP instruction.

Vn.<T>.

Vn.<T>[index].

bits 0-4 indicates register: Vn bits 5-8 indicates arrangement: <T>.

scalar floating point.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

Not registers, but flags that can be combined with regular register constants to indicate extended register conversion.

integer.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

to differentiate ZR/SP, REG_RSP&0x1f = 31.

Special registers, after subtracting obj.RBaseARM64, bit 12 indicates a special register and the low bits select the register.

SIMD.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

General purpose registers, kept in the low bits of Prog.Reg.

environment for closures.

frame pointer.

G.

Register assignments: compiler allocates R0 up as temps compiler allocates register variables R7-R25 compiler allocates external registers R26 down compiler allocates register variables F7-F26 compiler allocates external registers F26 down.

Register assignments: compiler allocates R0 up as temps compiler allocates register variables R7-R25 compiler allocates external registers R26 down compiler allocates register variables F7-F26 compiler allocates external registers F26 down.

register variables allocated from here to REGMAX.

ARM64 platform register, unused in the Go toolchain.

ARM64 IP0, external linker may use as a scratch register in trampoline.

ARM64 IP1, external linker may use as a scratch register in trampoline.

Register assignments: compiler allocates R0 up as temps compiler allocates register variables R7-R25 compiler allocates external registers R26 down compiler allocates register variables F7-F26 compiler allocates external registers F26 down.

reserved for liblink.

ARM64 uses R31 as both stack pointer and zero register, depending on the instruction.

shift types.

set as the lower bound.

PSTATE fields.

Condition code, EQ, NE, etc.

DC.

must be the first one.

TLBI.

http://infocenter.arm.com/help/topic/com.arm.doc.ecm0665627/abi_sve_aadwarf_100985_0000_00_en.pdf.

go:generate stringer -type SpecialOperand -trimprefix SPOP_.