# Functions
ARM64RegisterArrangement constructs an ARM64 vector register arrangement.
ARM64RegisterExtension constructs an ARM64 register with extension or arrangement.
ARM64RegisterListOffset generates offset encoding according to AArch64 specification.
ARM64RegisterShift constructs an ARM64 register with shift operation.
ARM64Suffix handles the special suffix for the ARM64.
ARMConditionCodes handles the special condition code situation for the ARM.
ARMMRCOffset implements the peculiar encoding of the MRC and MCR instructions.
GetARM64SpecialOperand returns the internal representation of a special operand.
IsARM64ADR reports whether the op (as defined by an arm64.A* constant) is one of the comparison instructions that require special handling.
IsARM64CASP reports whether the op (as defined by an arm64.A* constant) is one of the CASP-like instructions, and its 2nd destination is a register pair that require special handling.
IsARM64CMP reports whether the op (as defined by an arm64.A* constant) is one of the comparison instructions that require special handling.
IsARM64STLXR reports whether the op (as defined by an arm64.A* constant) is one of the STLXR-like instructions that require special handling.
IsARM64TBL reports whether the op (as defined by an arm64.A* constant) is one of the TBL-like instructions and one of its inputs does not fit into prog.Reg, so require special handling.
IsARMBFX reports whether the op (as defined by an arm.A* constant) is one the BFX-like instructions which are in the form of "op $width, $LSB, (Reg,) Reg".
IsARMCMP reports whether the op (as defined by an arm.A* constant) is one of the comparison instructions that require special handling.
IsARMFloatCmp reports whether the op is a floating comparison instruction.
IsARMMRC reports whether the op (as defined by an arm.A* constant) is MRC or MCR.
IsARMMULA reports whether the op (as defined by an arm.A* constant) is MULA, MULS, MMULA, MMULS, MULABB, MULAWB or MULAWT, the 4-operand instructions.
IsARMSTREX reports whether the op (as defined by an arm.A* constant) is one of the STREX-like instructions that require special handling.
IsLoong64CMP reports whether the op (as defined by an loong64.A* constant) is one of the CMP instructions that require special handling.
IsLoong64MUL reports whether the op (as defined by an loong64.A* constant) is one of the MUL/DIV/REM instructions that require special handling.
IsLoong64RDTIME reports whether the op (as defined by an loong64.A* constant) is one of the RDTIMELW/RDTIMEHW/RDTIMED instructions that require special handling.
IsMIPSCMP reports whether the op (as defined by an mips.A* constant) is one of the CMP instructions that require special handling.
IsMIPSMUL reports whether the op (as defined by an mips.A* constant) is one of the MUL/DIV/REM/MADD/MSUB instructions that require special handling.
IsPPC64CMP reports whether the op (as defined by an ppc64.A* constant) is one of the CMP instructions that require special handling.
IsPPC64NEG reports whether the op (as defined by an ppc64.A* constant) is one of the NEG-like instructions that require special handling.
IsRISCV64AMO reports whether the op (as defined by a riscv.A* constant) is one of the AMO instructions that requires special handling.
ParseARMCondition parses the conditions attached to an ARM instruction.
Set configures the architecture specified by GOARCH and returns its representation.
# Constants
Pseudo-registers whose names are the constant name without the leading R.
Pseudo-registers whose names are the constant name without the leading R.
Pseudo-registers whose names are the constant name without the leading R.
Pseudo-registers whose names are the constant name without the leading R.