package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ Clock divider bypass enable bit.
+ Card Status.
+ Card Status.
+ Card Status.
+ Card Status.
+ Command response received (CRC check failed).
+ CCRCFAIL flag clear bit.
+ Command CRC Fail Interrupt Enable.
+ Clock divide factor.
+ Clock enable bit.
+ Command transfer in progress.
+ CCommand Acting Interrupt Enable.
+ Command argument.
+ Command Index.
+ Command response received (CRC check passed).
+ CMDREND flag clear bit.
+ Command Response Received Interrupt Enable.
+ Command sent (no response required).
+ CMDSENT flag clear bit.
+ Command Sent Interrupt Enable.
+ Command path state machine (CPSM) Enable bit.
+ Command response timeout.
+ CTIMEOUT flag clear bit.
+ Command TimeOut Interrupt Enable.
+ Data count value.
+ Data end (data counter, SDIDCOUNT, is zero).
+ DATAEND flag clear bit.
+ Data End Interrupt Enable.
+ Data length value.
+ Data timeout period..
+ Data block sent/received (CRC check passed).
+ DBCKEND flag clear bit.
+ Data Block End Interrupt Enable.
+ DBLOCKSIZE[3:0] bits (Data block size).
+ Data block sent/received (CRC check failed).
+ DCRCFAIL flag clear bit.
+ Data CRC Fail Interrupt Enable.
+ DMA enabled bit.
+ Data transfer direction selection.
+ Data transfer enabled bit.
+ Data timeout.
+ DTIMEOUT flag clear bit.
+ Data TimeOut Interrupt Enable.
+ Data transfer mode selection.
+ Remaining number of words to be written to or read from the FIFO.
+ Receive and transmit FIFO data.
+ HW Flow Control enable.
+ SDMMC_CK dephasing selection bit.
+ PWRCTRL[1:0] bits (Power supply control bits).
+ Power saving configuration bit.
+ Read wait mode.
+ Read wait start.
+ Read wait stop.
+ Data receive in progress.
+ Data receive acting interrupt enabled.
+ Data available in receive FIFO.
+ Data available in Rx FIFO interrupt Enable.
+ Receive FIFO empty.
+ Rx FIFO Empty interrupt Enable.
+ Receive FIFO full.
+ Rx FIFO Full interrupt Enable.
+ Receive FIFO Half Full: there are at least 8 words in the FIFO.
+ Rx FIFO Half Full interrupt Enable.
+ Received FIFO overrun error.
+ RXOVERR flag clear bit.
+ Rx FIFO OverRun Error Interrupt Enable.
+ SD I/O enable functions.
+ SDIO interrupt received.
+ SDIOIT flag clear bit.
+ SDIO Mode Interrupt Received interrupt Enable.
+ SD I/O suspend command.
+ Start bit not detected on all data signals in wide bus mode.
+ STBITERR flag clear bit.
+ Data transmit in progress.
+ Data Transmit Acting Interrupt Enable.
+ Data available in transmit FIFO.
+ Data available in Tx FIFO interrupt Enable.
+ Transmit FIFO empty.
+ Tx FIFO Empty interrupt Enable.
+ Transmit FIFO full.
+ Tx FIFO Full interrupt Enable.
+ Transmit FIFO Half Empty: at least 8 words can be written into the FIFO.
+ Tx FIFO Half Empty interrupt Enable.
+ Transmit FIFO underrun error.
+ TXUNDERR flag clear bit.
+ Tx FIFO UnderRun Error Interrupt Enable.
+ CPSM Waits for Interrupt Request.
+ CPSM Waits for ends of data transfer (CmdPend internal signal).
+ WAITRESP[1:0] bits (Wait for response bits).
+ WIDBUS[1:0] bits (Wide bus mode enable bit).
# Variables
emgo:const.