package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ AWDCH[7:0] Analog watchdog channel selection.
+ Analog watchdog.
+ Analog watchdog interrupt enable.
+ AWFORD[1:0] Analog watchdog Sinc filter order on channel y.
+ AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y.
+ Analog watchdog fast mode select.
+ AWHT[23:0] Analog watchdog high threshold.
+ AWHTF[15:8] Analog watchdog high threshold error on given channels.
+ AWLT[23:0] Analog watchdog low threshold.
+ AWLTF[7:0] Analog watchdog low threshold error on given channels.
+ BKAWH[3:0] Break signal assignment to analog watchdog high threshold event.
+ BKAWL[3:0] Break signal assignment to analog watchdog low threshold event.
+ BKSCD[3:0] Break signal assignment for short circuit detector on channel y.
+ Channel y enable.
+ Serial inputs selection for channel y.
+ Clock absence detector enable on channel y.
+ CKABF[7:0] Clock absence flag.
+ Clock absence interrupt enable.
+ CKOUTDIV[7:0] output serial clock divider.
+ Output serial clock source selection.
+ CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag.
+ CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag.
+ CLRCKABF[7:0] Clear the clock absence flag.
+ Clear the injected conversion overrun flag.
+ Clear the regular conversion overrun flag.
+ CLRSCSDF[7:0] Clear the short circuit detector flag.
+ CNVCNT[27:0]: 28-bit timer counting conversion time.
+ DATMPX[1:0] Input data multiplexer for channel y.
+ DATPACK[1:0] Data packing mode.
+ DFSDM enable.
+ Global enable for DFSDM interface.
+ DTRBS[4:0] Data right bit-shift for channel y.
+ EXCH[7:0] Extreme detector channel selection.
+ EXMAX[23:0] Extreme detector maximum value.
+ EXMAXCH[2:0] Extreme detector maximum data channel.
+ EXMIN[23:0] Extreme detector minimum value.
+ EXMINCH[2:0] Extreme detector minimum data channel.
+ Fast conversion mode selection.
+ FORD[2:0] Sinc filter order.
+ FOSR[9:0] Sinc filter oversampling ratio (decimation rate).
+ INDAT0[31:16] Input data for channel y or channel (y+1).
+ INDAT0[15:0] Input data for channel y.
+ IOSR[7:0] Integrator oversampling ratio (averaging length).
+ JCHG[7:0] Injected channel group selection.
+ Injected conversion in progress status.
+ JDATA[23:0] Injected group conversion data.
+ JDATACH[2:0] Injected channel most recently converted.
+ DMA channel enabled to read data for the injected channel group.
+ End of injected conversion flag.
+ Injected end of conversion interrupt enable.
+ JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions.
+ JEXTSEL[2:0]Trigger signal selection for launching injected conversions.
+ Injected conversion overrun flag.
+ Injected data overrun interrupt enable.
+ Scanning conversion in continuous mode selection for injected conversions.
+ Start the conversion of the injected group of channels.
+ Launch an injected conversion synchronously with DFSDMx JSWSTART trigger.
+ OFFSET[23:0] 24-bit calibration offset for channel y.
+ RCH[2:0] Regular channel selection.
+ Regular conversion in progress status.
+ Continuous mode selection for regular conversions.
+ RDATA[23:0] Regular channel conversion data.
+ RDATACH[2:0] Regular channel most recently converted.
+ DMA channel enabled to read data for the regular conversion.
+ End of regular conversion flag.
+ Regular end of conversion interrupt enable.
+ Regular conversion overrun flag.
+ Regular data overrun interrupt enable.
+ RPEND Regular channel pending data.
+ Software start of a conversion on the regular channel.
+ Launch regular conversion synchronously with DFSDMx.
+ Short circuit detector enable on channel y.
+ SCDF[7:0] Short circuit detector flag.
+ Short circuit detector interrupt enable.
+ SCDT[7:0] Short circuit detector threshold for channel y.
+ SITP[1:0] Serial interface type for channel y.
+ SPICKSEL[1:0] SPI clock select for channel y.
# Variables
emgo:const.
emgo:const.
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emgo:const.
emgo:const.