package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ ADC calibration.
+ ADC differential mode for calibration.
+ ADC disable.
+ ADC enable.
+ ADC ready flag.
+ ADC multimode master ready flag.
+ ADC multimode slave ready flag.
+ ADC ready interrupt.
+ ADC group regular conversion start.
+ ADC group regular conversion stop.
+ ADC voltage regulator enable.
+ ADC data alignement.
+ ADC low power auto wait.
+ ADC analog watchdog 1 flag.
+ ADC multimode master analog watchdog 1 flag.
+ ADC multimode slave analog watchdog 1 flag.
+ ADC analog watchdog 1 monitored channel selection.
+ ADC analog watchdog 1 enable on scope ADC group regular.
+ ADC analog watchdog 1 interrupt.
+ ADC analog watchdog 1 monitoring a single channel or all channels.
+ ADC analog watchdog 2 flag.
+ ADC multimode master analog watchdog 2 flag.
+ ADC multimode slave analog watchdog 2 flag.
+ ADC analog watchdog 2 monitored channel selection.
+ ADC analog watchdog 2 interrupt.
+ ADC analog watchdog 3 flag.
+ ADC multimode master analog watchdog 3 flag.
+ ADC multimode slave analog watchdog 3 flag.
+ ADC analog watchdog 3 monitored channel selection.
+ ADC analog watchdog 3 interrupt.
+ ADC calibration factor in differential mode.
+ ADC calibration factor in single-ended mode.
+ ADC common clock source and prescaler (prescaler only for clock source synchronous).
+ ADC group regular continuous conversion mode.
+ ADC deep power down enable.
+ ADC multimode delay between 2 sampling phases.
+ ADC group regular sequencer discontinuous mode.
+ ADC group regular sequencer discontinuous number of ranks.
+ ADC DMA transfer configuration.
+ ADC DMA transfer enable.
+ ADC multimode mode selection.
+ ADC group regular end of unitary conversion flag.
+ ADC multimode master group regular end of unitary conversion flag.
+ ADC multimode slave group regular end of unitary conversion flag.
+ ADC group regular end of unitary conversion interrupt.
+ ADC group regular end of sequence conversions flag.
+ ADC multimode master group regular end of sequence conversions flag.
+ ADC multimode slave group regular end of sequence conversions flag.
+ ADC group regular end of sequence conversions interrupt.
+ ADC group regular end of sampling flag.
+ ADC multimode master group regular end of sampling flag.
+ ADC multimode slave group regular end of sampling flag.
+ ADC group regular end of sampling interrupt.
+ ADC group regular external trigger polarity.
+ ADC group regular external trigger source.
+ ADC Analog watchdog 1 threshold high.
+ ADC analog watchdog 2 threshold high.
+ ADC analog watchdog 3 threshold high.
+ ADC group injected conversion start.
+ ADC group injected conversion stop.
+ ADC group injected automatic trigger mode.
+ ADC analog watchdog 1 enable on scope ADC group injected.
+ ADC group injected sequencer rank 1 conversion data.
+ ADC group injected sequencer discontinuous mode.
+ ADC group injected end of unitary conversion flag.
+ ADC multimode master group injected end of unitary conversion flag.
+ ADC multimode slave group injected end of unitary conversion flag.
+ ADC group injected end of unitary conversion interrupt.
+ ADC group injected end of sequence conversions flag.
+ ADC multimode master group injected end of sequence conversions flag.
+ ADC multimode slave group injected end of sequence conversions flag.
+ ADC group injected end of sequence conversions interrupt.
+ ADC group injected external trigger polarity.
+ ADC group injected external trigger source.
+ ADC group injected sequencer scan length.
+ ADC oversampler enable on scope ADC group injected.
+ ADC group injected contexts queue disable.
+ ADC group injected contexts queue mode.
+ ADC group injected contexts queue overflow flag.
+ ADC multimode master group injected contexts queue overflow flag.
+ ADC multimode slave group injected contexts queue overflow flag.
+ ADC group injected contexts queue overflow interrupt.
+ ADC group injected sequencer rank 1.
+ ADC group injected sequencer rank 2.
+ ADC group injected sequencer rank 3.
+ ADC group injected sequencer rank 4.
+ ADC group regular sequencer scan length.
+ ADC analog watchdog 1 threshold low.
+ ADC analog watchdog 2 threshold low.
+ ADC analog watchdog 3 threshold low.
+ ADC multimode DMA transfer enable.
+ ADC multimode DMA transfer configuration.
+ ADC offset number 1 offset level.
+ ADC offset number 1 channel selection.
+ ADC offset number 1 enable.
+ ADC group regular overrun flag.
+ ADC multimode master group regular overrun flag.
+ ADC multimode slave group regular overrun flag.
+ ADC group regular overrun interrupt.
+ ADC group regular overrun configuration.
+ ADC oversampling ratio.
+ ADC oversampling shift.
+ ADC common clock prescaler, only for clock source asynchronous.
+ ADC group regular conversion data.
+ ADC multimode master group regular conversion data.
+ ADC multimode slave group regular conversion data.
+ ADC data resolution.
+ ADC oversampler enable on scope ADC group regular.
+ ADC oversampling mode managing interlaced conversions of ADC group regular and group injected.
+ ADC channel 0 sampling time selection.
+ ADC channel 1 sampling time selection.
+ ADC channel 10 sampling time selection.
+ ADC channel 11 sampling time selection.
+ ADC channel 12 sampling time selection.
+ ADC channel 13 sampling time selection.
+ ADC channel 14 sampling time selection.
+ ADC channel 15 sampling time selection.
+ ADC channel 16 sampling time selection.
+ ADC channel 17 sampling time selection.
+ ADC channel 18 sampling time selection.
+ ADC channel 2 sampling time selection.
+ ADC channel 3 sampling time selection.
+ ADC channel 4 sampling time selection.
+ ADC channel 5 sampling time selection.
+ ADC channel 6 sampling time selection.
+ ADC channel 7 sampling time selection.
+ ADC channel 8 sampling time selection.
+ ADC channel 9 sampling time selection.
+ ADC group regular sequencer rank 1.
+ ADC group regular sequencer rank 10.
+ ADC group regular sequencer rank 11.
+ ADC group regular sequencer rank 12.
+ ADC group regular sequencer rank 13.
+ ADC group regular sequencer rank 14.
+ ADC group regular sequencer rank 15.
+ ADC group regular sequencer rank 16.
+ ADC group regular sequencer rank 2.
+ ADC group regular sequencer rank 3.
+ ADC group regular sequencer rank 4.
+ ADC group regular sequencer rank 5.
+ ADC group regular sequencer rank 6.
+ ADC group regular sequencer rank 7.
+ ADC group regular sequencer rank 8.
+ ADC group regular sequencer rank 9.
+ ADC oversampling discontinuous mode (triggered mode) for ADC group regular.
+ ADC internal path to temperature sensor enable.
+ ADC internal path to battery voltage enable.
+ ADC internal path to VrefInt enable.