Categorygithub.com/ziutek/emgoegpathsrcstm32ol1xx_mdri
package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
Versions
1
Dependencies
4
Dependents
0
Files
1.3k SLOC

# Constants

+ AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits).
Bit 0.
Bit 1.
Bit 10.
Bit 11.
Bit 12.
Bit 13.
Bit 14.
Bit 15.
Bit 18.
Bit 19.
Bit 2.
Bit 20.
Bit 21.
Bit 22.
Bit 23.
Bit 24.
Bit 25.
Bit 27.
Bit 28.
Bit 29.
Bit 3.
Bit 30.
+ Bit 16.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
Bit 8.
Bit 9.
+ CH0b selection bit.
+ CH10b selection bit.
+ CH11b selection bit.
+ CH12b selection bit.
+ CH1b selection bit.
+ CH2b selection bit.
+ CH3b selection bit.
+ CH6b selection bit.
+ CH7b selection bit.
+ CH8b selection bit.
+ CH9b selection bit.
+ GR10-1 selection bit.
+ GR10-2 selection bit.
+ GR10-3 selection bit.
+ GR10-4 selection bit.
+ GR4-1 selection bit.
+ GR4-2 selection bit.
+ GR4-3 selection bit.
+ GR4-4 selection bit.
+ GR5-1 selection bit.
+ GR5-2 selection bit.
+ GR5-3 selection bit.
+ GR5-4 selection bit.
+ GR6-1 selection bit.
+ GR6-2 selection bit.
+ GR6-3 selection bit.
+ GR6-4 selection bit.
+ Input capture 1.
+ IC1Z[3:0] bits (Input Capture 1 select bits).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Input capture 2.
+ IC2Z[3:0] bits (Input Capture 2 select bits).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Input capture 3.
+ IC3Z[3:0] bits (Input Capture 3 select bits).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Input capture 4.
+ IC4Z[3:0] bits (Input Capture 4 select bits).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ PA[15:0] Port A Hysteresis selection.
+ PA[15:0] Port A analog switch mode selection.
+ PA[15:0] Port A channel masking.
+ PA[15:0] Port A channel identification for capture.
Bit 0.
Bit 0.
Bit 0.
Bit 0.
Bit 1.
Bit 1.
Bit 1.
Bit 1.
Bit 10.
Bit 10.
Bit 10.
Bit 10.
Bit 11.
Bit 11.
Bit 11.
Bit 11.
Bit 12.
Bit 12.
Bit 12.
Bit 12.
Bit 13.
Bit 13.
Bit 13.
Bit 13.
Bit 14.
Bit 14.
Bit 14.
Bit 14.
Bit 15.
Bit 15.
Bit 15.
Bit 15.
Bit 2.
Bit 2.
Bit 2.
Bit 2.
Bit 3.
Bit 3.
Bit 3.
Bit 3.
Bit 4.
Bit 4.
Bit 4.
Bit 4.
Bit 5.
Bit 5.
Bit 5.
Bit 5.
Bit 6.
Bit 6.
Bit 6.
Bit 6.
Bit 7.
Bit 7.
Bit 7.
Bit 7.
Bit 8.
Bit 8.
Bit 8.
Bit 8.
Bit 9.
Bit 9.
Bit 9.
Bit 9.
+ PB[15:0] Port B Hysteresis selection.
+ PB[15:0] Port B analog switch mode selection.
+ PB[15:0] Port B channel masking.
+ PB[15:0] Port B channel identification for capture.
Bit 0.
Bit 0.
Bit 0.
Bit 0.
Bit 1.
Bit 1.
Bit 1.
Bit 1.
Bit 10.
Bit 10.
Bit 10.
Bit 10.
Bit 11.
Bit 11.
Bit 11.
Bit 11.
Bit 12.
Bit 12.
Bit 12.
Bit 12.
Bit 13.
Bit 13.
Bit 13.
Bit 13.
Bit 14.
Bit 14.
Bit 14.
Bit 14.
Bit 15.
Bit 15.
Bit 15.
Bit 15.
Bit 2.
Bit 2.
Bit 2.
Bit 2.
Bit 3.
Bit 3.
Bit 3.
Bit 3.
Bit 4.
Bit 4.
Bit 4.
Bit 4.
Bit 5.
Bit 5.
Bit 5.
Bit 5.
Bit 6.
Bit 6.
Bit 6.
Bit 6.
Bit 7.
Bit 7.
Bit 7.
Bit 7.
Bit 8.
Bit 8.
Bit 8.
Bit 8.
Bit 9.
Bit 9.
Bit 9.
Bit 9.
+ PC[15:0] Port C Hysteresis selection.
+ PC[15:0] Port C analog switch mode selection.
+ PC[15:0] Port C channel masking.
+ PC[15:0] Port C channel identification for capture.
Bit 0.
Bit 0.
Bit 0.
Bit 0.
Bit 1.
Bit 1.
Bit 1.
Bit 1.
Bit 10.
Bit 10.
Bit 10.
Bit 10.
Bit 11.
Bit 11.
Bit 11.
Bit 11.
Bit 12.
Bit 12.
Bit 12.
Bit 12.
Bit 13.
Bit 13.
Bit 13.
Bit 13.
Bit 14.
Bit 14.
Bit 14.
Bit 14.
Bit 15.
Bit 15.
Bit 15.
Bit 15.
Bit 2.
Bit 2.
Bit 2.
Bit 2.
Bit 3.
Bit 3.
Bit 3.
Bit 3.
Bit 4.
Bit 4.
Bit 4.
Bit 4.
Bit 5.
Bit 5.
Bit 5.
Bit 5.
Bit 6.
Bit 6.
Bit 6.
Bit 6.
Bit 7.
Bit 7.
Bit 7.
Bit 7.
Bit 8.
Bit 8.
Bit 8.
Bit 8.
Bit 9.
Bit 9.
Bit 9.
Bit 9.
+ PD[15:0] Port D Hysteresis selection.
Bit 0.
Bit 1.
Bit 10.
Bit 11.
Bit 12.
Bit 13.
Bit 14.
Bit 15.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
Bit 8.
Bit 9.
PE[15:0] Port E Hysteresis selection.
Bit 0.
Bit 1.
Bit 10.
Bit 11.
Bit 12.
Bit 13.
Bit 14.
Bit 15.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
Bit 8.
Bit 9.
+ PF[15:0] Port F Hysteresis selection.
+ PF[15:0] Port F analog switch mode selection.
+ PF[15:0] Port F channel masking.
+ PF[15:0] Port F channel identification for capture.
Bit 0.
Bit 0.
Bit 0.
Bit 0.
Bit 1.
Bit 1.
Bit 1.
Bit 1.
Bit 10.
Bit 10.
Bit 10.
Bit 10.
Bit 11.
Bit 11.
Bit 11.
Bit 11.
Bit 12.
Bit 12.
Bit 12.
Bit 12.
Bit 13.
Bit 13.
Bit 13.
Bit 13.
Bit 14.
Bit 14.
Bit 14.
Bit 14.
Bit 15.
Bit 15.
Bit 15.
Bit 15.
Bit 2.
Bit 2.
Bit 2.
Bit 2.
Bit 3.
Bit 3.
Bit 3.
Bit 3.
Bit 4.
Bit 4.
Bit 4.
Bit 4.
Bit 5.
Bit 5.
Bit 5.
Bit 5.
Bit 6.
Bit 6.
Bit 6.
Bit 6.
Bit 7.
Bit 7.
Bit 7.
Bit 7.
Bit 8.
Bit 8.
Bit 8.
Bit 8.
Bit 9.
Bit 9.
Bit 9.
Bit 9.
+ PG[15:0] Port G Hysteresis selection.
+ PG[15:0] Port G analog switch mode selection.
+ PG[15:0] Port G channel masking.
+ PG[15:0] Port G channel identification for capture.
Bit 0.
Bit 0.
Bit 0.
Bit 0.
Bit 1.
Bit 1.
Bit 1.
Bit 1.
Bit 10.
Bit 10.
Bit 10.
Bit 10.
Bit 11.
Bit 11.
Bit 11.
Bit 11.
Bit 12.
Bit 12.
Bit 12.
Bit 12.
Bit 13.
Bit 13.
Bit 13.
Bit 13.
Bit 14.
Bit 14.
Bit 14.
Bit 14.
Bit 15.
Bit 15.
Bit 15.
Bit 15.
Bit 2.
Bit 2.
Bit 2.
Bit 2.
Bit 3.
Bit 3.
Bit 3.
Bit 3.
Bit 4.
Bit 4.
Bit 4.
Bit 4.
Bit 5.
Bit 5.
Bit 5.
Bit 5.
Bit 6.
Bit 6.
Bit 6.
Bit 6.
Bit 7.
Bit 7.
Bit 7.
Bit 7.
Bit 8.
Bit 8.
Bit 8.
Bit 8.
Bit 9.
Bit 9.
Bit 9.
Bit 9.
+ I/O Switch control mode.
+ TIM[3:0] bits (Timers select bits).
Bit 0.
Bit 1.
+ ADC analog switch selection for internal node to COMP1.

# Variables

emgo:const.

# Structs

# Type aliases