package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ ADC1 clock enable.
+ ADC1 clock enabled in sleep mode.
+ ADC1 reset.
+ AES clock enable.
+ AES clock enabled in sleep mode.
+ AES reset.
+ Comparator interface clock enable.
+ Comparator interface clock enabled in sleep mode.
+ Comparator interface reset.
+ CRC clock enable.
+ CRC clock enabled in sleep mode.
+ CRC reset.
+ Clock Security System Interrupt Clear.
+ Clock Security System Interrupt flag.
+ Clock Security System enable.
+ DAC interface clock enable.
+ DAC interface clock enabled in sleep mode.
+ DAC interface reset.
+ DMA1 clock enable.
+ DMA1 clock enabled in sleep mode.
+ DMA1 reset.
+ DMA2 clock enable.
+ DMA2 clock enabled in sleep mode.
+ DMA2 reset.
+ FLITF clock enable (has effect only when.
+ Flash Interface clock enabled in sleep mode.
+ FLITF reset.
+ FSMC clock enable.
+ FSMC clock enabled in sleep mode.
+ FSMC reset.
+ GPIO port A clock enable.
+ GPIO port A clock enabled in sleep mode.
+ GPIO port A reset.
+ GPIO port B clock enable.
+ GPIO port B clock enabled in sleep mode.
+ GPIO port B reset.
+ GPIO port C clock enable.
+ GPIO port C clock enabled in sleep mode.
+ GPIO port C reset.
+ GPIO port D clock enable.
+ GPIO port D clock enabled in sleep mode.
+ GPIO port D reset.
+ GPIO port E clock enable.
+ GPIO port E clock enabled in sleep mode.
+ GPIO port E reset.
+ GPIO port F clock enable.
+ GPIO port F clock enabled in sleep mode.
+ GPIO port F reset.
+ GPIO port G clock enable.
+ GPIO port G clock enabled in sleep mode.
+ GPIO port G reset.
+ GPIO port H clock enable.
+ GPIO port H clock enabled in sleep mode.
+ GPIO port H reset.
+ HPRE[3:0] bits (AHB prescaler).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
SYSCLK not divided.
SYSCLK divided by 128.
SYSCLK divided by 16.
SYSCLK divided by 2.
SYSCLK divided by 256.
SYSCLK divided by 4.
SYSCLK divided by 512.
SYSCLK divided by 64.
SYSCLK divided by 8.
+ External High Speed clock Bypass.
+ External High Speed clock enable.
+ External High Speed clock ready flag.
+ HSE Ready Interrupt Clear.
+ HSE Ready Interrupt flag.
+ HSE Ready Interrupt Enable.
+ Internal High Speed clock Calibration.
+ Internal High Speed clock enable.
+ Internal High Speed clock ready flag.
+ HSI Ready Interrupt Clear.
+ HSI Ready Interrupt flag.
+ HSI Ready Interrupt Enable.
+ Internal High Speed clock trimming.
+ I2C 1 clock enable.
+ I2C 1 clock enabled in sleep mode.
+ I2C 1 reset.
+ I2C 2 clock enable.
+ I2C 2 clock enabled in sleep mode.
+ I2C 2 reset.
+ Independent Watchdog reset flag.
+ LCD clock enable.
+ LCD clock enabled in sleep mode.
+ LCD reset.
+ Low-Power reset flag.
+ External Low Speed oscillator Bypass.
+ LSE CSS Interrupt flag.
+ LSE CSS Interrupt Clear.
+ External Low Speed oscillator CSS Detected.
+ LSE CSS Interrupt Enable.
+ External Low Speed oscillator CSS Enable.
+ External Low Speed oscillator enable.
+ External Low Speed oscillator Ready.
+ LSE Ready Interrupt Clear.
+ LSE Ready Interrupt flag.
+ LSE Ready Interrupt Enable.
+ Internal Low Speed oscillator enable.
+ Internal Low Speed oscillator Ready.
+ LSI Ready Interrupt Clear.
+ LSI Ready Interrupt flag.
+ LSI Ready Interrupt Enable.
MCO Clock divided by 1.
MCO Clock divided by 16.
MCO Clock divided by 2.
MCO Clock divided by 4.
MCO Clock divided by 8.
External 1-25 MHz oscillator clock selected.
Internal 16 MHz RC oscillator clock selected.
LSE selected.
LSI selected.
Internal Medium Speed RC oscillator clock selected.
No clock.
PLL clock divided.
System clock selected.
+ MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler).
Bit 0.
Bit 1.
Bit 2.
+ MCO[2:0] bits (Microcontroller Clock Output).
Bit 0.
Bit 1.
Bit 2.
+ Internal Multi Speed clock Calibration.
+ Internal Multi Speed clock enable.
+ Internal Multi Speed clock Range.
Internal Multi Speed clock Range 65.536 KHz.
Internal Multi Speed clock Range 131.072 KHz.
Internal Multi Speed clock Range 262.144 KHz.
Internal Multi Speed clock Range 524.288 KHz.
Internal Multi Speed clock Range 1.048 MHz.
Internal Multi Speed clock Range 2.097 MHz.
Internal Multi Speed clock Range 4.194 MHz.
+ Internal Multi Speed clock ready flag.
+ MSI Ready Interrupt Clear.
+ MSI Ready Interrupt flag.
+ MSI Ready Interrupt Enable.
+ Internal Multi Speed clock trimming.
+ Option Bytes Loader reset flag.
+ PIN reset flag.
+ PLLDIV[1:0] bits (PLL Output Division).
Bit0.
Bit1.
PLL clock output = CKVCO / 1.
PLL clock output = CKVCO / 2.
PLL clock output = CKVCO / 3.
PLL clock output = CKVCO / 4.
+ PLLMUL[3:0] bits (PLL multiplication factor).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
PLL input clock * 12.
PLL input clock * 16.
PLL input clock * 24.
PLL input clock * 3.
PLL input clock * 32.
PLL input clock * 4.
PLL input clock * 48.
PLL input clock * 6.
PLL input clock * 8.
+ PLL enable.
+ PLL clock ready flag.
+ PLL Ready Interrupt Clear.
+ PLL Ready Interrupt flag.
+ PLL Ready Interrupt Enable.
+ PLL entry clock source.
HSE as PLL entry clock source.
HSI as PLL entry clock source.
+ POR/PDR reset flag.
+ PRE1[2:0] bits (APB1 prescaler).
Bit 0.
Bit 1.
Bit 2.
HCLK not divided.
HCLK divided by 16.
HCLK divided by 2.
HCLK divided by 4.
HCLK divided by 8.
+ PRE2[2:0] bits (APB2 prescaler).
Bit 0.
Bit 1.
Bit 2.
HCLK not divided.
HCLK divided by 16.
HCLK divided by 2.
HCLK divided by 4.
HCLK divided by 8.
+ Power interface clock enable.
+ Power interface clock enabled in sleep mode.
+ Power interface reset.
+ Remove reset flag.
+ RTC clock enable.
+ RTC/LCD Prescaler.
Bit0.
Bit1.
+ RTC reset.
+ RTCSEL[1:0] bits (RTC clock source selection).
Bit 0.
Bit 1.
HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock.
LSE oscillator clock used as RTC clock.
LSI oscillator clock used as RTC clock.
No clock.
+ SDIO clock enable.
+ SDIO clock enabled in sleep mode.
+ SDIO reset.
+ Software Reset flag.
+ SPI1 clock enable.
+ SPI1 clock enabled in sleep mode.
+ SPI1 reset.
+ SPI 2 clock enable.
+ SPI 2 clock enabled in sleep mode.
+ SPI 2 reset.
+ SPI 3 clock enable.
+ SPI 3 clock enabled in sleep mode.
+ SPI 3 reset.
+ SRAM clock enabled in sleep mode.
+ SW[1:0] bits (System clock Switch).
Bit 0.
Bit 1.
HSE selected as system clock.
HSI selected as system clock.
MSI selected as system clock.
PLL selected as system clock.
+ SWS[1:0] bits (System Clock Switch Status).
Bit 0.
Bit 1.
HSE oscillator used as system clock.
HSI oscillator used as system clock.
MSI oscillator used as system clock.
PLL used as system clock.
+ System Configuration SYSCFG clock enable.
+ System Configuration SYSCFG clock enabled in sleep mode.
+ System Configuration SYSCFG reset.
+ TIM10 interface clock enable.
+ TIM10 interface clock enabled in sleep mode.
+ TIM10 reset.
+ TIM11 Timer clock enable.
+ TIM11 Timer clock enabled in sleep mode.
+ TIM11 reset.
+ Timer 2 clock enabled.
+ Timer 2 clock enabled in sleep mode.
+ Timer 2 reset.
+ Timer 3 clock enable.
+ Timer 3 clock enabled in sleep mode.
+ Timer 3 reset.
+ Timer 4 clock enable.
+ Timer 4 clock enabled in sleep mode.
+ Timer 4 reset.
+ Timer 5 clock enable.
+ Timer 5 clock enabled in sleep mode.
+ Timer 5 reset.
+ Timer 6 clock enable.
+ Timer 6 clock enabled in sleep mode.
+ Timer 6 reset.
+ Timer 7 clock enable.
+ Timer 7 clock enabled in sleep mode.
+ Timer 7 reset.
+ TIM9 interface clock enable.
+ TIM9 interface clock enabled in sleep mode.
+ TIM9 reset.
+ UART 4 clock enable.
+ UART 4 clock enabled in sleep mode.
+ UART 4 reset.
+ UART 5 clock enable.
+ UART 5 clock enabled in sleep mode.
+ UART 5 reset.
+ USART1 clock enable.
+ USART1 clock enabled in sleep mode.
+ USART1 reset.
+ USART 2 clock enable.
+ USART 2 clock enabled in sleep mode.
+ USART 2 reset.
+ USART 3 clock enable.
+ USART 3 clock enabled in sleep mode.
+ USART 3 reset.
+ USB clock enable.
+ USB clock enabled in sleep mode.
+ USB reset.
+ Window Watchdog clock enable.
+ Window Watchdog clock enabled in sleep mode.
+ Window Watchdog reset.
+ Window watchdog reset flag.
# Variables
emgo:const.