package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ Automatic Output enable.
+ Auto-reload preload enable.
+ Break2 Generation.
+ Break2 interrupt Flag.
+ Break Generation.
+ Break interrupt enable.
+ Break interrupt Flag.
+ Break enable for Break2.
+ Break Filter for Break2.
+ Break Polarity for Break2.
+ Break enable.
+ Break Filter for Break1.
+ Break Polarity.
+ Capture/Compare 1 DMA request enable.
+ Capture/Compare 1 output enable.
+ Capture/Compare 1 Generation.
+ Capture/Compare 1 interrupt enable.
+ Capture/Compare 1 interrupt Flag.
+ Capture/Compare 1 Complementary output enable.
+ Capture/Compare 1 Complementary output Polarity.
+ Capture/Compare 1 Overcapture Flag.
+ Capture/Compare 1 output Polarity.
+ CC1S[1:0] bits (Capture/Compare 1 Selection).
Bit 0.
Bit 1.
+ Capture/Compare 2 DMA request enable.
+ Capture/Compare 2 output enable.
+ Capture/Compare 2 Generation.
+ Capture/Compare 2 interrupt enable.
+ Capture/Compare 2 interrupt Flag.
+ Capture/Compare 2 Complementary output enable.
+ Capture/Compare 2 Complementary output Polarity.
+ Capture/Compare 2 Overcapture Flag.
+ Capture/Compare 2 output Polarity.
+ CC2S[1:0] bits (Capture/Compare 2 Selection).
Bit 0.
Bit 1.
+ Capture/Compare 3 DMA request enable.
+ Capture/Compare 3 output enable.
+ Capture/Compare 3 Generation.
+ Capture/Compare 3 interrupt enable.
+ Capture/Compare 3 interrupt Flag.
+ Capture/Compare 3 Complementary output enable.
+ Capture/Compare 3 Complementary output Polarity.
+ Capture/Compare 3 Overcapture Flag.
+ Capture/Compare 3 output Polarity.
+ CC3S[1:0] bits (Capture/Compare 3 Selection).
Bit 0.
Bit 1.
+ Capture/Compare 4 DMA request enable.
+ Capture/Compare 4 output enable.
+ Capture/Compare 4 Generation.
+ Capture/Compare 4 interrupt enable.
+ Capture/Compare 4 interrupt Flag.
+ Capture/Compare 4 Complementary output Polarity.
+ Capture/Compare 4 Overcapture Flag.
+ Capture/Compare 4 output Polarity.
+ CC4S[1:0] bits (Capture/Compare 4 Selection).
Bit 0.
Bit 1.
+ Capture/Compare 5 output enable.
+ Capture/Compare 5 output Polarity.
+ Capture/Compare 6 output enable.
+ Capture/Compare 6 output Polarity.
+ Capture/Compare DMA Selection.
+ Capture/Compare Preloaded Control.
+ Capture/Compare 5 Value.
+ Capture/Compare Control Update Selection.
+ Counter enable.
+ CKD[1:0] bits (clock division).
Bit 0.
Bit 1.
+ CMS[1:0] bits (Center-aligned mode selection).
Bit 0.
Bit 1.
+ COM DMA request enable.
+ Capture/Compare Control Update Generation.
+ COM interrupt enable.
+ COM interrupt Flag.
+ DBA[4:0] bits (DMA Base Address).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ DBL[4:0] bits (DMA Burst Length).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ Direction.
+ DMA register for burst accesses.
+ DTG[0:7] bits (Dead-Time Generator set-up).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
+ External clock enable.
+ ETF[3:0] bits (External trigger filter).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ External trigger polarity.
+ ETPS[1:0] bits (External trigger prescaler).
Bit 0.
Bit 1.
Group Channel 5 and Channel 1.
Group Channel 5 and Channel 2.
Group Channel 5 and Channel 3.
+ IC1F[3:0] bits (Input Capture 1 Filter).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ IC1PSC[1:0] bits (Input Capture 1 Prescaler).
Bit 0.
Bit 1.
+ IC2F[3:0] bits (Input Capture 2 Filter).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ IC2PSC[1:0] bits (Input Capture 2 Prescaler).
Bit 0.
Bit 1.
+ IC3F[3:0] bits (Input Capture 3 Filter).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ IC3PSC[1:0] bits (Input Capture 3 Prescaler).
Bit 0.
Bit 1.
+ IC4F[3:0] bits (Input Capture 4 Filter).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ IC4PSC[1:0] bits (Input Capture 4 Prescaler).
Bit 0.
Bit 1.
+ ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap).
Bit 0.
Bit 1.
+ LOCK[1:0] bits (Lock Configuration).
Bit 0.
Bit 1.
+ MMS[2:0] bits (Master Mode Selection).
Bit 0.
Bit 1.
Bit 2.
+ MMS[2:0] bits (Master Mode Selection).
Bit 0.
Bit 1.
Bit 2.
Bit 2.
+ Main Output enable.
+ Master/slave mode.
+ Output Compare 1Clear Enable.
+ Output Compare 1 Fast enable.
+ OC1M[2:0] bits (Output Compare 1 Mode).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Output Compare 1 Preload enable.
+ Output Compare 2 Clear Enable.
+ Output Compare 2 Fast enable.
+ OC2M[2:0] bits (Output Compare 2 Mode).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Output Compare 2 Preload enable.
+ Output Compare 3 Clear Enable.
+ Output Compare 3 Fast enable.
+ OC3M[2:0] bits (Output Compare 3 Mode).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Output Compare 3 Preload enable.
+ Output Compare 4 Clear Enable.
+ Output Compare 4 Fast enable.
+ OC4M[2:0] bits (Output Compare 4 Mode).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Output Compare 4 Preload enable.
+ Output Compare 5 Clear Enable.
+ Output Compare 5 Fast enable.
+ OC5M[2:0] bits (Output Compare 5 Mode).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Output Compare 5 Preload enable.
+ Output Compare 4 Clear Enable.
+ Output Compare 4 Fast enable.
+ OC4M[2:0] bits (Output Compare 4 Mode).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Output Compare 4 Preload enable.
+ OCREF clear selection.
+ Output Idle state 1 (OC1 output).
+ Output Idle state 1 (OC1N output).
+ Output Idle state 2 (OC2 output).
+ Output Idle state 2 (OC2N output).
+ Output Idle state 3 (OC3 output).
+ Output Idle state 3 (OC3N output).
+ Output Idle state 4 (OC4 output).
+ Output Idle state 4 (OC4 output).
+ Output Idle state 4 (OC4 output).
+ One pulse mode.
+ Off-State Selection for Idle mode.
+ Off-State Selection for Run mode.
+ Repetition Counter Value.
+ SMS[2:0] bits (Slave mode selection).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Trigger DMA request enable.
+ Trigger Generation.
+ TI1 Selection.
+ TI4_RMP[1:0] bits (TIM5 Input 4 remap).
Bit 0.
Bit 1.
+ Trigger interrupt enable.
+ Trigger interrupt Flag.
+ TS[2:0] bits (Trigger selection).
Bit 0.
Bit 1.
Bit 2.
+ Update DMA request enable.
+ Update disable.
+ Update Generation.
+ Update interrupt enable.
+ Update interrupt Flag.
+ UIF status bit.
+ Update request source.