package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ ACCMOD[1:0] bits (Access mode).
Bit 0.
Bit 1.
+ ADDHLD[3:0] bits (Address-hold phase duration).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ ADDSET[3:0] bits (Address setup phase duration).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Asynchronous wait.
+ ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
+ ATTHOLD3[7:0] bits (Attribute memory 3 hold time).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
+ ATTSET3[7:0] bits (Attribute memory 3 setup time).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
+ ATTWAIT3[7:0] bits (Attribute memory 3 wait time).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
+ Burst enable bit.
+ BUSTURN[3:0] bits (Bus turnaround phase duration).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Busy status.
+ CAS[1:0] bits (CAS latency).
Bit 0.
Bit 1.
+ Write burst enable.
+ Continous clock enable.
+ CLKDIV[3:0] bits (Clock divide ratio).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ COUNT[12:0] bits (Refresh timer count).
+ CRAM page size.
Bit 0.
Bit 1.
Bit 2.
+ Clear refresh error flag.
+ Command target 1.
+ Command target 2.
+ DATAST [3:0] bits (Data-phase duration).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
+ DATLA[3:0] bits (Data latency).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ ACCMOD[1:0] bits (Access mode).
Bit 0.
Bit 1.
+ ADDHLD[3:0] bits (Address-hold phase duration).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ ADDSET[3:0] bits (Address setup phase duration).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ BUSTURN[3:0] bits (Bus turnaround phase duration).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ ECC result.
+ ECC computation logic enable bit.
+ ECCPS[2:0] bits (ECC page size).
Bit 0.
Bit 1.
Bit 2.
+ DATAST [3:0] bits (Data-phase duration).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
+ Extended mode enable.
+ Flash access enable.
+ FIFO empty.
+ Interrupt Falling Edge detection Enable bit.
+ Interrupt Falling Edge status.
+ Interrupt Level detection Enable bit.
+ Interrupt Level status.
+ Interrupt Rising Edge detection Enable bit.
+ Interrupt Rising Edge status.
+ Memory bank enable bit.
+ MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
+ MEMHOLD3[7:0] bits (Common memory 3 hold time).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
+ MEMSET3[7:0] bits (Common memory 3 setup time).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
+ MEMWAIT3[7:0] bits (Common memory 3 wait time).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
Bit 5.
Bit 6.
Bit 7.
+ MODE[2:0] bits (Command mode).
Bit 0.
Bit 1.
Bit 2.
+ MODES1[1:0]bits (Status mode for bank 1).
Bit 0.
Bit 1.
+ MODES2[1:0]bits (Status mode for bank 2).
Bit 0.
Bit 1.
+ MRD[12:0] bits (Mode register definition).
+ MTYP[1:0] bits (Memory type).
Bit 0.
Bit 1.
+ Address/data multiplexing enable bit.
+ MWID[1:0] bits (Memory data bus width).
Bit 0.
Bit 1.
+ Number of internal bank.
+ NC[1:0] bits (Number of column bits).
Bit 0.
Bit 1.
+ NR[1:0] bits (Number of row bits).
Bit 0.
Bit 1.
+ NRFS[3:0] bits (Number of auto-refresh).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ PC Card/NAND Flash memory bank enable bit.
+ Memory type.
+ Wait feature enable bit.
+ PWID[1:0] bits (NAND Flash databus width).
Bit 0.
Bit 1.
+ Read burst.
+ Refresh error flag.
+ RES interupt enable.
+ Write protection.
Bit 0.
Bit 1.
+ SDRAM clock configuration.
Bit 0.
Bit 1.
+ NR[1:0] bits (Number of row bits).
Bit 0.
Bit 1.
+ TAR[3:0] bits (ALE to RE delay).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ TCLR[3:0] bits (CLE to RE delay).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ TMRD[3:0] bits (Load mode register to active).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ TRAS[3:0] bits (Self refresh time).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ TRC[2:0] bits (Row cycle delay).
Bit 0.
Bit 1.
Bit 2.
+ TRP[2:0] bits (Row to column delay).
Bit 0.
Bit 1.
Bit 2.
+ TRP[2:0] bits (Row precharge delay).
Bit 0.
Bit 1.
Bit 2.
+ TRC[2:0] bits (Write recovery delay).
Bit 0.
Bit 1.
Bit 2.
+ TXSR[3:0] bits (Exit self refresh).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Wait timing configuration.
+ Wait enable bit.
+ Wait signal polarity bit.
+ Write FIFO Disable.
+ Write protection.
+ Wrapped burst mode support.
+ Write enable bit.