package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ Address-Aligned beats.
+ Address enable.
+ Address enable.
+ Address enable.
+ Abnormal interrupt summary.
+ Abnormal interrupt summary enable.
+ Automatic Pad/CRC stripping.
+ Broadcast frame disable.
+ Back-off limit: random integer number (r) of slot time delays before rescheduling.
k = min (n, 1).
k = min (n, 10).
k = min (n, 4).
k = min (n, 8).
+ CR clock range: 6 cases.
+ Counters Reset.
HCLK:150-168 MHz; MDC clock= HCLK/102.
HCLK:20-35 MHz; MDC clock= HCLK/16.
HCLK:35-60 MHz; MDC clock= HCLK/26.
HCLK:60-100 MHz; MDC clock= HCLK/42.
HCLK:100-150 MHz; MDC clock= HCLK/62.
+ Carrier sense disable (during transmission).
+ Counter Stop Rollover.
+ Wake-up frame filter register data.
+ DMA arbitration scheme.
+ DA Inverse filtering.
+ Defferal check.
+ Disable flushing of received frames.
+ Duplex mode.
+ Descriptor Skip Length.
+ Disable Dropping of TCP/IP checksum error frames.
+ Error bits status.
Error bits 0-Rx DMA, 1-Tx DMA.
Error bits 0-data buffer, 1-desc.
Error bits 0-write trnsf, 1-read transfr.
+ Enhanced Descriptor Enable.
+ Early receive interrupt enable.
+ Early receive status.
+ Early transmit interrupt enable.
+ Early transmit status.
+ Fixed Burst.
+ Fatal bus error interrupt enable.
+ Fatal bus error status.
+ Flow control busy/backpressure activate.
+ Forward error frames.
+ Fast ethernet speed.
+ 4xPBL mode.
+ Flush transmit FIFO.
+ Forward undersized good frames.
+ Global Unicast.
+ Hash multicast.
+ Hash or perfect filter.
+ Host receive buffer address pointer.
+ Host receive descriptor address pointer.
+ Host transmit buffer address pointer.
+ Host transmit descriptor address pointer.
+ Hash table high.
+ Hash table low.
+ Hash unicast.
+ Inter-frame gap.
Minimum IFG between frames during transmission is 40Bit.
Minimum IFG between frames during transmission is 48Bit.
Minimum IFG between frames during transmission is 56Bit.
Minimum IFG between frames during transmission is 64Bit.
Minimum IFG between frames during transmission is 72Bit.
Minimum IFG between frames during transmission is 80Bit.
Minimum IFG between frames during transmission is 88Bit.
Minimum IFG between frames during transmission is 96Bit.
+ IP Checksum offload.
+ Jabber disable.
+ loopback mode.
+ MAC address0 high.
+ MAC address0 low.
+ MAC address1 high.
+ MAC address1 low.
+ MAC address1 high.
+ MAC address2 low.
+ MAC address3 high.
+ MAC address3 low.
+ MII busy.
+ Mask byte control: bits to mask for comparison of the MAC Address bytes.
+ Mask byte control.
+ Mask byte control.
Mask MAC Address high reg bits [15:8].
Mask MAC Address high reg bits [15:8].
Mask MAC Address high reg bits [15:8].
Mask MAC Address high reg bits [7:0].
Mask MAC Address high reg bits [7:0].
Mask MAC Address high reg bits [7:0].
Mask MAC Address low reg bits [15:8].
Mask MAC Address low reg bits [15:8].
Mask MAC Address low reg bits [15:8].
Mask MAC Address low reg bits [23:16].
Mask MAC Address low reg bits [23:16].
Mask MAC Address low reg bits [23:16].
Mask MAC Address low reg bits [31:24].
Mask MAC Address low reg bits [31:24].
Mask MAC Address low reg bits [31:24].
Mask MAC Address low reg bits [7:0].
Mask MAC Address low reg bits [70].
Mask MAC Address low reg bits [70].
+ MMC Counter Freeze.
+ MMC counter Full-Half preset.
+ MMC counter preset.
+ MII data: read/write data from/to PHY.
+ Number of frames missed by the application.
+ Number of frames missed by the controller.
+ MMC status.
+ MMC status.
+ MMC transmit status.
+ MMC receive status.
+ Magic Packet Enable.
+ Magic Packet Received.
+ MII register in the selected PHY.
+ MII write.
+ Normal interrupt summary.
+ Normal interrupt summary enable.
+ Overflow bit for FIFO overflow counter.
+ Overflow bit for missed frame counter.
+ operate on second frame.
+ Physical layer address.
+ Pass all mutlicast.
+ Programmable burst length.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 16.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 1.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 2.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 32.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 4.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 128.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 16.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 32.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 4.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 64.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 8.
maximum number of beats to be transferred in one TxDMA (or both) transaction is 8.
+ Pass control frames: 3 cases.
MAC filters all control frames from reaching the application.
MAC forwards all control frames to application even if they fail the Address Filter.
MAC forwards control frames that pass the Address Filter..
+ Power Down.
+ Pause low threshold: 4 cases.
Pause time minus 144 slot times.
Pause time minus 256 slot times.
Pause time minus 28 slot times.
Pause time minus 4 slot times.
+ Promiscuous mode.
+ PMT interrupt mask.
+ PMT status.
+ PMT status.
+ Pause time.
+ Receive all.
+ Receive buffer unavailable interrupt enable.
+ Receive buffer unavailable status.
+ Retry disable.
+ RxDMA PBL.
maximum number of beats to be transferred in one RxDMA transaction is 16.
maximum number of beats to be transferred in one RxDMA transaction is 1.
maximum number of beats to be transferred in one RxDMA transaction is 2.
maximum number of beats to be transferred in one RxDMA transaction is 32.
maximum number of beats to be transferred in one RxDMA transaction is 4.
maximum number of beats to be transferred in one RxDMA transaction is 128.
maximum number of beats to be transferred in one RxDMA transaction is 16.
maximum number of beats to be transferred in one RxDMA transaction is 32.
maximum number of beats to be transferred in one RxDMA transaction is 4.
maximum number of beats to be transferred in one RxDMA transaction is 64.
maximum number of beats to be transferred in one RxDMA transaction is 8.
maximum number of beats to be transferred in one RxDMA transaction is 8.
+ Receiver enable.
+ Number of frames received with alignment (dribble) error.
+ Mask the interrupt when when Rx alignment error counter reaches half the maximum value.
+ Set when Rx alignment error counter reaches half the maximum value.
+ Receive flow control enable.
+ Number of frames received with CRC error..
+ Mask the interrupt when Rx crc error counter reaches half the maximum value.
+ Set when Rx crc error counter reaches half the maximum value.
+ Number of good unicast frames received..
+ Mask the interrupt when Rx good unicast frames counter reaches half the maximum value.
+ Set when Rx good unicast frames counter reaches half the maximum value.
+ Receive interrupt enable.
+ Receive own disable.
+ Receive Overflow interrupt enable.
+ Reset on Read.
+ Receive overflow status.
+ Receive poll demand.
+ Receive process state.
Running - closing descriptor.
Running - fetching the Rx descriptor.
Running - queuing the recieve frame into host memory.
Stopped - Reset or Stop Rx Command issued.
Suspended - Rx Descriptor unavailable.
Running - waiting for packet.
+ Receive process stopped interrupt enable.
+ Receive process stopped status.
+ Receive status.
+ Receive store and forward.
+ receive threshold control.
threshold level of the MTL Receive FIFO is 128 Bytes.
threshold level of the MTL Receive FIFO is 32 Bytes.
threshold level of the MTL Receive FIFO is 64 Bytes.
threshold level of the MTL Receive FIFO is 96 Bytes.
+ Rx Tx priority ratio.
Rx Tx priority ratio.
Rx Tx priority ratio.
Rx Tx priority ratio.
Rx Tx priority ratio.
+ Receive watchdog timeout interrupt enable.
+ Receive watchdog timeout status.
+ Source address.
+ Source address.
+ Source address.
+ Source address filter enable.
+ SA inverse filtering.
+ Software reset.
+ Start/stop receive.
+ Start of receive list.
+ Start/stop transmission command.
+ Start of transmit list.
+ System Time Positive or negative time.
+ System Time second.
+ System Time sub-seconds.
+ System time Sub-second increment value.
+ Transmit buffer unavailable interrupt enable.
+ Transmit buffer unavailable status.
+ Transmitter enable.
+ Transmit flow control enable.
+ Number of good frames transmitted..
+ Mask the interrupt when Tx good frame count counter reaches half the maximum value.
+ Number of successfully transmitted frames after more than a single collision in Half-duplex mode..
+ Mask the interrupt when Tx good multi col counter reaches half the maximum value.
+ Set when Tx good multi col counter reaches half the maximum value.
+ Set when Tx good frame count counter reaches half the maximum value.
+ Number of successfully transmitted frames after a single collision in Half-duplex mode..
+ Mask the interrupt when Tx good single col counter reaches half the maximum value.
+ Set when Tx good single col counter reaches half the maximum value.
+ Transmit interrupt enable.
+ Transmit jabber timeout interrupt enable.
+ Transmit jabber timeout status.
+ Transmit poll demand.
+ Transmit process state.
Running - closing Rx descriptor.
Running - fetching the Tx descriptor.
Running - reading the data from host memory.
Stopped - Reset or Stop Tx Command issued.
Suspended - Tx Descriptor unavailabe.
Running - waiting for status.
+ Transmit process stopped interrupt enable.
+ Transmit process stopped status.
+ Transmit status.
+ Time stamp addend.
+ Addend register update.
+ Time stamp clock node type.
+ Time stamp enable.
+ Transmit store and forward.
+ Time stamp fine or coarse update.
+ Time stamp interrupt trigger enable.
+ Time stamp PTP packet snooping for version2 format enable.
+ Time stamp snapshot for all received frames enable.
+ Time stamp snapshot for event message enable.
+ Time stamp snapshot for IPv4 frames enable.
+ Time stamp snapshot for IPv6 frames enable.
+ Time stamp snapshot for message relevant to master enable.
+ Time stamp seconds overflow.
+ Time stamp snapshot for PTP over ethernet frames enable.
+ Time stamp Sub-seconds rollover.
+ Time stamp initialize.
+ Time stamp update.
+ Time stamp trigger interrupt mask.
+ Time stamp trigger status.
+ Time-stamp trigger status.
+ Time stamp target time reached.
+ Time stamp update Positive or negative time.
+ Time stamp update seconds.
+ Time stamp update sub-seconds.
+ Transmit threshold control.
threshold level of the MTL Transmit FIFO is 128 Bytes.
threshold level of the MTL Transmit FIFO is 16 Bytes.
threshold level of the MTL Transmit FIFO is 192 Bytes.
threshold level of the MTL Transmit FIFO is 24 Bytes.
threshold level of the MTL Transmit FIFO is 256 Bytes.
threshold level of the MTL Transmit FIFO is 32 Bytes.
threshold level of the MTL Transmit FIFO is 40 Bytes.
threshold level of the MTL Transmit FIFO is 64 Bytes.
+ Target time stamp high.
+ Target time stamp low.
+ Transmit Underflow interrupt enable.
+ Transmit underflow status.
+ Unicast pause frame detect.
+ Use separate PBL.
+ 12-bit VLAN tag comparison.
+ VLAN tag identifier (for receive frames).
+ Watchdog disable.
+ Wake-Up Frame Enable.
+ Wake-Up Frame Filter Register Pointer Reset.
+ Wake-Up Frame Received.
+ Zero-quanta pause disable.
# Variables
emgo:const.