package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ ADC12 regular channel EXT13 remap.
+ ADC12 regular channel EXT15 remap.
+ ADC12 regular channel EXT2 remap.
+ ADC12 regular channel EXT3 remap.
+ ADC12 regular channel EXT5 remap.
+ ADC12 injected channel JEXT13 remap.
+ ADC12 injected channel JEXT3 remap.
+ ADC12 injected channel JEXT6 remap.
ADC2 and ADC4 DMA remap.
+ ADC34 regular channel EXT15 remap.
+ ADC34 regular channel EXT5 remap.
+ ADC34 regular channel EXT6 remap.
+ ADC34 injected channel JEXT11 remap.
+ ADC34 injected channel JEXT14 remap.
+ ADC34 injected channel JEXT5 remap.
+ Disables the adddress parity check on RAM.
+ DAC1 Trigger1 remap.
+ DMA remap mask.
+ Encoder Mode.
TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively.
TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively.
+ EXTI 0 configuration.
PA[0] pin.
PB[0] pin.
PC[0] pin.
PD[0] pin.
PE[0] pin.
PF[0] pin.
PG[0] pin.
PH[0] pin.
+ EXTI 1 configuration.
PA[1] pin.
PB[1] pin.
PC[1] pin.
PD[1] pin.
PE[1] pin.
PF[1] pin.
PG[1] pin.
PH[1] pin.
+ EXTI 2 configuration.
PA[2] pin.
PB[2] pin.
PC[2] pin.
PD[2] pin.
PE[2] pin.
PF[2] pin.
PG[2] pin.
+ EXTI 3 configuration.
PA[3] pin.
PB[3] pin.
PC[3] pin.
PD[3] pin.
PE[3] pin.
PE[3] pin.
PG[3] pin.
+ Floating Point Unit Interrupt Enable.
+ I2C PB6 Fast mode plus.
+ I2C PB7 Fast mode plus.
+ I2C PB8 Fast mode plus.
+ I2C PB9 Fast mode plus.
+ I2C1 Fast mode plus.
+ I2C2 Fast mode plus.
+ I2C3 Fast mode plus.
+ Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMx.
+ SYSCFG_Memory Remap Config.
Bit 0.
Bit 1.
Bit 2.
+ ICODE SRAM Write protection page 0.
+ ICODE SRAM Write protection page 1.
+ ICODE SRAM Write protection page 10.
+ ICODE SRAM Write protection page 11.
+ ICODE SRAM Write protection page 12.
+ ICODE SRAM Write protection page 13.
+ ICODE SRAM Write protection page 14.
+ ICODE SRAM Write protection page 15.
+ ICODE SRAM Write protection page 2.
+ ICODE SRAM Write protection page 3.
+ ICODE SRAM Write protection page 4.
+ ICODE SRAM Write protection page 5.
+ ICODE SRAM Write protection page 6.
+ ICODE SRAM Write protection page 7.
+ ICODE SRAM Write protection page 8.
+ ICODE SRAM Write protection page 9.
+ Enables and locks the PVD connection with TIMx Break Input, as well as the PVDE and PLS[2:0] in the PWR_CR register.
+ Enables and locks the SRAM_PARITY error signal with Break Input of TIMx.
+ SRAM Parity error flag.
+ Timer 1 ITR3 selection.
Timer 16 DMA remap.
Timer 17 DMA remap.
Timer 6 / DAC1 Ch1 DMA remap.
Timer 7 / DAC1 Ch2 DMA remap.
+ USB interrupt remap.
# Variables
emgo:const.