package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ ADC1/ ADC2 clock enable.
+ ADC1 & ADC2 reset.
+ ADC3/ ADC4 clock enable.
+ ADC3 & ADC4 reset.
+ ADCPRE12[8:4] bits.
ADC12 PLL clock divided by 1.
ADC12 PLL clock divided by 10.
ADC12 PLL clock divided by 12.
ADC12 PLL clock divided by 128.
ADC12 PLL clock divided by 16.
ADC12 PLL clock divided by 2.
ADC12 PLL clock divided by 256.
ADC12 PLL clock divided by 32.
ADC12 PLL clock divided by 4.
ADC12 PLL clock divided by 6.
ADC12 PLL clock divided by 64.
ADC12 PLL clock divided by 8.
ADC12 clock disabled, ADC12 can use AHB clock.
+ ADCPRE34[13:5] bits.
ADC34 PLL clock divided by 1.
ADC34 PLL clock divided by 10.
ADC34 PLL clock divided by 12.
ADC34 PLL clock divided by 128.
ADC34 PLL clock divided by 16.
ADC34 PLL clock divided by 2.
ADC34 PLL clock divided by 256.
ADC34 PLL clock divided by 32.
ADC34 PLL clock divided by 4.
ADC34 PLL clock divided by 6.
ADC34 PLL clock divided by 64.
ADC34 PLL clock divided by 8.
ADC34 clock disabled, ADC34 can use AHB clock.
+ Backup domain software reset.
+ CAN clock enable.
+ CAN reset.
+ CRC clock enable.
+ Clock Security System Interrupt Clear.
+ Clock Security System Interrupt flag.
+.
+ DAC 1 clock enable.
+ DAC 1 reset.
+ DMA1 clock enable.
+ DMA2 clock enable.
+ FLITF clock enable.
+ FMC clock enable.
+ FMC reset.
+ GPIOA clock enable.
+ GPIOA reset.
+ GPIOB clock enable.
+ GPIOB reset.
+ GPIOC clock enable.
+ GPIOC reset.
+ GPIOD clock enable.
+ GPIOD reset.
+ GPIOE clock enable.
+ GPIOE reset.
+ GPIOF clock enable.
+ GPIOF reset.
+ GPIOG clock enable.
+ GPIOG reset.
+ GPIOH clock enable.
+ GPIOH reset.
+ HPRE[3:0] bits (AHB prescaler).
SYSCLK not divided.
SYSCLK divided by 128.
SYSCLK divided by 16.
SYSCLK divided by 2.
SYSCLK divided by 256.
SYSCLK divided by 4.
SYSCLK divided by 512.
SYSCLK divided by 64.
SYSCLK divided by 8.
+.
+.
+.
+ HSE Ready Interrupt Clear.
+ HSE Ready Interrupt flag.
+ HSE Ready Interrupt Enable.
+.
+.
+.
+ HSI Ready Interrupt Clear.
+ HSI Ready Interrupt flag.
+ HSI Ready Interrupt Enable.
+.
+ I2C 1 clock enable.
+ I2C 1 reset.
I2C1SW bits.
HSI oscillator clock used as I2C1 clock source.
System clock selected as I2C1 clock source.
+ I2C 2 clock enable.
+ I2C 2 reset.
I2C2SW bits.
HSI oscillator clock used as I2C2 clock source.
System clock selected as I2C2 clock source.
+ I2C 3 clock enable.
+ I2C 3 reset.
I2C3SW bits.
HSI oscillator clock used as I2C3 clock source.
System clock selected as I2C3 clock source.
+ I2CSW bits.
+ I2S external clock source selection.
External clock selected as I2S clock source.
System clock selected as I2S clock source.
+ Independent Watchdog reset flag.
+ Low-Power reset flag.
+ External Low Speed oscillator [2:0] bits.
External Low Speed oscillator Bypass.
+ LSEDRV[1:0] bits (LSE Osc.
External Low Speed oscillator enable.
External Low Speed oscillator Ready.
+ LSE Ready Interrupt Clear.
+ LSE Ready Interrupt flag.
+ LSE Ready Interrupt Enable.
+ Internal Low Speed oscillator enable.
+ Internal Low Speed oscillator Ready.
+ LSI Ready Interrupt Clear.
+ LSI Ready Interrupt flag.
+ LSI Ready Interrupt Enable.
+ MCO[2:0] bits (Microcontroller Clock Output).
HSE clock selected as MCO source.
HSI clock selected as MCO source.
LSE clock selected as MCO source.
LSI clock selected as MCO source.
No clock.
PLL clock divided by 2 selected as MCO source.
System clock selected as MCO source.
+ MCOPRE[3:0] bits (Microcontroller Clock Output Prescaler).
MCO is divided by 1.
MCO is divided by 128.
MCO is divided by 16.
MCO is divided by 2.
MCO is divided by 32.
MCO is divided by 4.
MCO is divided by 64.
MCO is divided by 8.
+ OBL reset flag.
+ PIN reset flag.
+ PLLMUL[3:0] bits (PLL multiplication factor).
PLL input clock10.
PLL input clock*11.
PLL input clock*12.
PLL input clock*13.
PLL input clock*14.
PLL input clock*15.
PLL input clock*16.
PLL input clock*2.
PLL input clock*3.
PLL input clock*4.
PLL input clock*5.
PLL input clock*6.
PLL input clock*7.
PLL input clock*8.
PLL input clock*9.
+ Do not divide PLL to MCO.
+.
+.
+ PLL Ready Interrupt Clear.
+ PLL Ready Interrupt flag.
+ PLL Ready Interrupt Enable.
+ PLL entry clock source.
HSE/PREDIV clock selected as PLL entry clock source.
HSI/PREDIV clock as PLL entry clock source.
+ HSE divider for PLL entry.
HSE/PREDIV clock not divided for PLL entry.
HSE/PREDIV clock divided by 2 for PLL entry.
+ POR/PDR reset flag.
+ PRE1[2:0] bits (APB1 prescaler).
HCLK not divided.
HCLK divided by 16.
HCLK divided by 2.
HCLK divided by 4.
HCLK divided by 8.
+ PRE2[2:0] bits (APB2 prescaler).
HCLK not divided.
HCLK divided by 16.
HCLK divided by 2.
HCLK divided by 4.
HCLK divided by 8.
+ PREDIV[3:0] bits.
PREDIV input clock not divided.
PREDIV input clock divided by 10.
PREDIV input clock divided by 11.
PREDIV input clock divided by 12.
PREDIV input clock divided by 13.
PREDIV input clock divided by 14.
PREDIV input clock divided by 15.
PREDIV input clock divided by 16.
PREDIV input clock divided by 2.
PREDIV input clock divided by 3.
PREDIV input clock divided by 4.
PREDIV input clock divided by 5.
PREDIV input clock divided by 6.
PREDIV input clock divided by 7.
PREDIV input clock divided by 8.
PREDIV input clock divided by 9.
+ PWR clock enable.
+ PWR reset.
+ Remove reset flag.
+ RTC clock enable.
+ RTCSEL[1:0] bits (RTC clock source selection).
HSE oscillator clock divided by 32 used as RTC clock.
LSE oscillator clock used as RTC clock.
LSI oscillator clock used as RTC clock.
No clock.
+ Software Reset flag.
+ SPI1 clock enable.
+ SPI1 reset.
+ SPI2 clock enable.
+ SPI2 reset.
+ SPI3 clock enable.
+ SPI3 reset.
+ SPI4 clock enable.
+ SPI4 reset.
+ SRAM interface clock enable.
+ SW[1:0] bits (System clock Switch).
HSE selected as system clock.
HSI selected as system clock.
PLL selected as system clock.
+ SWS[1:0] bits (System Clock Switch Status).
HSE oscillator used as system clock.
HSI oscillator used as system clock.
PLL used as system clock.
+ SYSCFG clock enable.
+ SYSCFG reset.
+ TIM15 clock enable.
+ TIM15 reset.
TIM15SW bits.
PCLK2 used as TIM15 clock source.
PLL clock used as TIM15 clock source.
+ TIM16 clock enable.
+ TIM16 reset.
TIM16SW bits.
PCLK2 used as TIM16 clock source.
PLL clock used as TIM16 clock source.
+ TIM17 clock enable.
+ TIM17 reset.
TIM17SW bits.
PCLK2 used as TIM17 clock source.
PLL clock used as TIM17 clock source.
+ TIM1 clock enable.
+ TIM1 reset.
TIM1SW bits.
PCLK2 used as TIM1 clock source.
PLL clock used as TIM1 clock source.
+ TIM20 clock enable.
+ TIM20 reset.
TIM20SW bits.
PCLK2 used as TIM20 clock source.
PLL clock used as TIM20 clock source.
+ Timer 2 clock enable.
+ Timer 2 reset.
+ TIM2SW bits.
PCLK1 used as TIM2 clock source.
PLL clock used as TIM2 clock source.
+ TIM34SW bits.
PCLK1 used as TIM3/TIM4 clock source.
PLL clock used as TIM3/TIM4 clock source.
+ Timer 3 clock enable.
+ Timer 3 reset.
+ Timer 4 clock enable.
+ Timer 4 reset.
+ Timer 6 clock enable.
+ Timer 6 reset.
+ Timer 7 clock enable.
+ Timer 7 reset.
+ TIM8 clock enable.
+ TIM8 reset.
TIM8SW bits.
PCLK2 used as TIM8 clock source.
PLL clock used as TIM8 clock source.
+ TIMSW bits.
+ TS clock enable.
+ TSC reset.
+ UART 4 clock enable.
+ UART 4 reset.
+ UART4SW[1:0] bits.
HSI oscillator clock used as UART4 clock source.
LSE oscillator clock used as UART4 clock source.
PCLK1 clock used as UART4 clock source.
System clock selected as UART4 clock source.
+ UART 5 clock enable.
+ UART 5 reset.
+ UART5SW[1:0] bits.
HSI oscillator clock used as UART5 clock source.
LSE oscillator clock used as UART5 clock source.
PCLK1 clock used as UART5 clock source.
System clock selected as UART5 clock source.
+ USART1 clock enable.
+ USART1 reset.
+ USART1SW[1:0] bits.
HSI oscillator clock used as USART1 clock source.
LSE oscillator clock used as USART1 clock source.
PCLK2 clock used as USART1 clock source.
System clock selected as USART1 clock source.
+ USART 2 clock enable.
+ USART 2 reset.
+ USART2SW[1:0] bits.
HSI oscillator clock used as USART2 clock source.
LSE oscillator clock used as USART2 clock source.
PCLK1 clock used as USART2 clock source.
System clock selected as USART2 clock source.
+ USART 3 clock enable.
+ USART 3 reset.
+ USART3SW[1:0] bits.
HSI oscillator clock used as USART3 clock source.
LSE oscillator clock used as USART3 clock source.
PCLK1 clock used as USART3 clock source.
System clock selected as USART3 clock source.
+ USB clock enable.
+ USB prescaler.
USB prescaler is PLL clock divided by 1.
USB prescaler is PLL clock divided by 1.5.
+ USB reset.
+ V1.8 power domain reset flag.
+ Window Watchdog clock enable.
+ Window Watchdog reset.
+ Window watchdog reset flag.
# Variables
emgo:const.