package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ ACCMOD[1:0] bits (Access mode).
+ ADDHLD[3:0] bits (Address-hold phase duration).
+ ADDSET[3:0] bits (Address setup phase duration).
+ Asynchronous wait.
+ ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time).
+ ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time).
+ ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time).
+ ATTHOLD2[7:0] bits (Attribute memory 2 hold time).
+ ATTHOLD3[7:0] bits (Attribute memory 3 hold time).
+ ATTHOLD4[7:0] bits (Attribute memory 4 hold time).
+ ATTSET2[7:0] bits (Attribute memory 2 setup time).
+ ATTSET3[7:0] bits (Attribute memory 3 setup time).
+ ATTSET4[7:0] bits (Attribute memory 4 setup time).
+ ATTWAIT2[7:0] bits (Attribute memory 2 wait time).
+ ATTWAIT3[7:0] bits (Attribute memory 3 wait time).
+ ATTWAIT4[7:0] bits (Attribute memory 4 wait time).
+ Burst enable bit.
+ BUSTURN[3:0] bits (Bus turnaround phase duration).
+ Write burst enable.
+ Continous clock enable.
+ CLKDIV[3:0] bits (Clock divide ratio).
+ DATAST [3:0] bits (Data-phase duration).
+ DATLA[3:0] bits (Data latency).
+ ACCMOD[1:0] bits (Access mode).
+ ADDHLD[3:0] bits (Address-hold phase duration).
+ ADDSET[3:0] bits (Address setup phase duration).
+ ECC result.
+ ECC result.
+ ECC computation logic enable bit.
+ ECC computation logic enable bit.
+ ECC computation logic enable bit.
+ ECCPS[1:0] bits (ECC page size).
+ ECCPS[2:0] bits (ECC page size).
+ ECCPS[2:0] bits (ECC page size).
+ CLKDIV[3:0] bits (Clock divide ratio).
+ DATAST [3:0] bits (Data-phase duration).
+ DATLA[3:0] bits (Data latency).
+ Extended mode enable.
+ Flash access enable.
+ FIFO empty.
+ FIFO empty.
+ FIFO empty.
+ Interrupt Falling Edge detection Enable bit.
+ Interrupt Falling Edge detection Enable bit.
+ Interrupt Falling Edge detection Enable bit.
+ Interrupt Falling Edge status.
+ Interrupt Falling Edge status.
+ Interrupt Falling Edge status.
+ Interrupt Level detection Enable bit.
+ Interrupt Level detection Enable bit.
+ Interrupt Level detection Enable bit.
+ Interrupt Level status.
+ Interrupt Level status.
+ Interrupt Level status.
+ IOHIZ4[7:0] bits (I/O 4 databus HiZ time).
+ IOHOLD4[7:0] bits (I/O 4 hold time).
+ IOSET4[7:0] bits (I/O 4 setup time).
+ IOWAIT4[7:0] bits (I/O 4 wait time).
+ Interrupt Rising Edge detection Enable bit.
+ Interrupt Rising Edge detection Enable bit.
+ Interrupt Rising Edge detection Enable bit.
+ Interrupt Rising Edge status.
+ Interrupt Rising Edge status.
+ Interrupt Rising Edge status.
+ Memory bank enable bit.
+ MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time).
+ MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time).
+ MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time).
+ MEMHOLD2[7:0] bits (Common memory 2 hold time).
+ MEMHOLD3[7:0] bits (Common memory 3 hold time).
+ MEMHOLD4[7:0] bits (Common memory 4 hold time).
+ MEMSET2[7:0] bits (Common memory 2 setup time).
+ MEMSET3[7:0] bits (Common memory 3 setup time).
+ MEMSET4[7:0] bits (Common memory 4 setup time).
+ MEMWAIT2[7:0] bits (Common memory 2 wait time).
+ MEMWAIT3[7:0] bits (Common memory 3 wait time).
+ MEMWAIT4[7:0] bits (Common memory 4 wait time).
+ MTYP[1:0] bits (Memory type).
+ Address/data multiplexing enable bit.
+ MWID[1:0] bits (Memory data bus width).
+ PC Card/NAND Flash memory bank enable bit.
+ PC Card/NAND Flash memory bank enable bit.
+ PC Card/NAND Flash memory bank enable bit.
+ Memory type.
+ Memory type.
+ Memory type.
+ Wait feature enable bit.
+ Wait feature enable bit.
+ Wait feature enable bit.
+ PWID[1:0] bits (NAND Flash databus width).
+ PWID[1:0] bits (NAND Flash databus width).
+ PWID[1:0] bits (NAND Flash databus width).
+ TAR[3:0] bits (ALE to RE delay).
+ TAR[3:0] bits (ALE to RE delay).
+ TAR[3:0] bits (ALE to RE delay).
+ TCLR[3:0] bits (CLE to RE delay).
+ TCLR[3:0] bits (CLE to RE delay).
+ TCLR[3:0] bits (CLE to RE delay).
+ Wait timing configuration.
+ Wait enable bit.
+ Wait signal polarity bit.
+ Wrapped burst mode support.
+ Write enable bit.