+ ADC 1 External Trigger Injected Conversion remapping.

+ ADC 1 External Trigger Regular Conversion remapping.

+ ADC 2 External Trigger Injected Conversion remapping.

+ ADC 2 External Trigger Regular Conversion remapping.

+ CAN_REMAP[1:0] bits (CAN Alternate function remapping).

Bit 0.

Bit 1.

CANRX mapped to PA11, CANTX mapped to PA12.

CANRX mapped to PB8, CANTX mapped to PB9.

CANRX mapped to PD0, CANTX mapped to PD1.

+ Event Output Enable.

+ EXTI 0 configuration.

PA[0] pin.

PB[0] pin.

PC[0] pin.

PD[0] pin.

PE[0] pin.

PF[0] pin.

PG[0] pin.

+ EXTI 1 configuration.

PA[1] pin.

PB[1] pin.

PC[1] pin.

PD[1] pin.

PE[1] pin.

PF[1] pin.

PG[1] pin.

+ EXTI 2 configuration.

PA[2] pin.

PB[2] pin.

PC[2] pin.

PD[2] pin.

PE[2] pin.

PF[2] pin.

PG[2] pin.

+ EXTI 3 configuration.

PA[3] pin.

PB[3] pin.

PC[3] pin.

PD[3] pin.

PE[3] pin.

PF[3] pin.

PG[3] pin.

+ I2C1 remapping.

+ Port D0/Port D1 mapping on OSC_IN/OSC_OUT.

+ PIN[3:0] bits (Pin selection).

Bit 0.

Bit 1.

Bit 2.

Bit 3.

Pin 0 selected.

Pin 1 selected.

Pin 10 selected.

Pin 11 selected.

Pin 12 selected.

Pin 13 selected.

Pin 14 selected.

Pin 15 selected.

Pin 2 selected.

Pin 3 selected.

Pin 4 selected.

Pin 5 selected.

Pin 6 selected.

Pin 7 selected.

Pin 8 selected.

Pin 9 selected.

+ PORT[2:0] bits (Port selection).

Bit 0.

Bit 1.

Bit 2.

Port A selected.

Port B selected.

Port C selected.

Port D selected.

Port E selected.

+ SPI1 remapping.

+ SWJ_CFG[2:0] bits (Serial Wire JTAG configuration).

Bit 0.

Bit 1.

Bit 2.

JTAG-DP Disabled and SW-DP Disabled.

JTAG-DP Disabled and SW-DP Enabled.

Full SWJ (JTAG-DP + SW-DP) but without JNTRST.

Full SWJ (JTAG-DP + SW-DP) : Reset State.

+ TIM1_REMAP[1:0] bits (TIM1 remapping).

Bit 0.

Bit 1.

Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12).

No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15).

Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1).

+ TIM2_REMAP[1:0] bits (TIM2 remapping).

Bit 0.

Bit 1.

Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11).

No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3).

Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3).

Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11).

+ TIM3_REMAP[1:0] bits (TIM3 remapping).

Bit 0.

Bit 1.

Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9).

No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1).

Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1).

+ TIM4_REMAP bit (TIM4 remapping).

+ TIM5 Channel4 Internal Remap.

+ USART1 remapping.

+ USART2 remapping.

+ USART3_REMAP[1:0] bits (USART3 remapping).

Bit 0.

Bit 1.

Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12).

No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14).

Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14).

emgo:const.