package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ ADC2 data.
+ A/D Converter ON / OFF.
+ Data Alignment.
+ Analog watchdog flag.
+ AWDCH[4:0] bits (Analog watchdog channel select bits).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ Analog watchdog enable on regular channels.
+ Analog Watchdog interrupt enable.
+ Enable the watchdog on a single channel in scan mode.
+ A/D Calibration.
+ Continuous Conversion.
+ Regular data.
+ Discontinuous mode on regular channels.
+ DISCNUM[2:0] bits (Discontinuous mode channel count).
Bit 0.
Bit 1.
Bit 2.
+ Direct Memory access mode.
+ DUALMOD[3:0] bits (Dual mode selection).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ End of conversion.
+ Interrupt enable for EOC.
+ EXTSEL[2:0] bits (External Event Select for regular group).
Bit 0.
Bit 1.
Bit 2.
+ External Trigger Conversion mode for regular channels.
+ Analog watchdog high threshold.
+ Automatic injected group conversion.
+ Analog watchdog enable on injected channels.
+ Injected data.
+ Discontinuous mode on injected channels.
+ Injected channel end of conversion.
+ Interrupt enable for injected channels.
+ JEXTSEL[2:0] bits (External event select for injected group).
Bit 0.
Bit 1.
Bit 2.
+ External Trigger Conversion mode for injected channels.
+ JL[1:0] bits (Injected Sequence length).
Bit 0.
Bit 1.
+ Data offset for injected channel 1.
+ Data offset for injected channel 2.
+ Data offset for injected channel 3.
+ Data offset for injected channel 4.
+ JSQ1[4:0] bits (1st conversion in injected sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ JSQ2[4:0] bits (2nd conversion in injected sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ JSQ3[4:0] bits (3rd conversion in injected sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ JSQ4[4:0] bits (4th conversion in injected sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ Injected channel Start flag.
+ Start Conversion of injected channels.
+ L[3:0] bits (Regular channel sequence length).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
+ Analog watchdog low threshold.
+ Reset Calibration.
+ Scan mode.
+ SMP0[2:0] bits (Channel 0 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP1[2:0] bits (Channel 1 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP10[2:0] bits (Channel 10 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP11[2:0] bits (Channel 11 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP12[2:0] bits (Channel 12 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP13[2:0] bits (Channel 13 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP14[2:0] bits (Channel 14 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP15[2:0] bits (Channel 15 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP16[2:0] bits (Channel 16 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP17[2:0] bits (Channel 17 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP2[2:0] bits (Channel 2 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP3[2:0] bits (Channel 3 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP4[2:0] bits (Channel 4 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP5[2:0] bits (Channel 5 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP6[2:0] bits (Channel 6 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP7[2:0] bits (Channel 7 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP8[2:0] bits (Channel 8 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SMP9[2:0] bits (Channel 9 Sample time selection).
Bit 0.
Bit 1.
Bit 2.
+ SQ1[4:0] bits (1st conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ10[4:0] bits (10th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ11[4:0] bits (11th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ12[4:0] bits (12th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ13[4:0] bits (13th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ14[4:0] bits (14th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ15[4:0] bits (15th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ16[4:0] bits (16th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ2[4:0] bits (2nd conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ3[4:0] bits (3rd conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ4[4:0] bits (4th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ5[4:0] bits (5th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ6[4:0] bits (6th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ7[4:0] bits (7th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ8[4:0] bits (8th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ SQ9[4:0] bits (9th conversion in regular sequence).
Bit 0.
Bit 1.
Bit 2.
Bit 3.
Bit 4.
+ Regular channel Start flag.
+ Start Conversion of regular channels.
+ Temperature Sensor and VREFINT Enable.