+ ADC 1 interface clock enable.

+ ADC 1 interface reset.

+ ADC 2 interface clock enable.

+ ADC 2 interface reset.

+ DMA1 clock enable.

+ ADC3 interface reset.

+ ADCPRE[1:0] bits (ADC prescaler).

Bit 0.

Bit 1.

PCLK2 divided by 2.

PCLK2 divided by 4.

PCLK2 divided by 6.

PCLK2 divided by 8.

+ Alternate Function I/O clock enable.

+ Alternate Function I/O reset.

+ Backup domain software reset.

+ Backup interface clock enable.

+ Backup interface reset.

+ CAN1 clock enable.

+ CAN1 reset.

+ CRC clock enable.

+ Clock Security System Interrupt Clear.

+ Clock Security System Interrupt flag.

+ Clock Security System enable.

+ DAC interface clock enable.

+ DAC interface reset.

+ DMA1 clock enable.

+ DMA2 clock enable.

+ FLITF clock enable.

+ FSMC clock enable.

+ HPRE[3:0] bits (AHB prescaler).

Bit 0.

Bit 1.

Bit 2.

Bit 3.

SYSCLK not divided.

SYSCLK divided by 128.

SYSCLK divided by 16.

SYSCLK divided by 2.

SYSCLK divided by 256.

SYSCLK divided by 4.

SYSCLK divided by 512.

SYSCLK divided by 64.

SYSCLK divided by 8.

+ External High Speed clock Bypass.

+ External High Speed clock enable.

+ External High Speed clock ready flag.

+ HSE Ready Interrupt Clear.

+ HSE Ready Interrupt flag.

+ HSE Ready Interrupt Enable.

+ Internal High Speed clock Calibration.

+ Internal High Speed clock enable.

+ Internal High Speed clock ready flag.

+ HSI Ready Interrupt Clear.

+ HSI Ready Interrupt flag.

+ HSI Ready Interrupt Enable.

+ Internal High Speed clock trimming.

+ I2C 1 clock enable.

+ I2C 1 reset.

+ I2C 2 clock enable.

+ I2C 2 reset.

+ I/O port A clock enable.

+ I/O port A reset.

+ I/O port B clock enable.

+ I/O port B reset.

+ I/O port C clock enable.

+ I/O port C reset.

+ I/O port D clock enable.

+ I/O port D reset.

+ I/O port E clock enable.

+ I/O port E reset.

+ I/O port F clock enable.

+ I/O port F reset.

+ I/O port G clock enable.

+ I/O port G reset.

+ Independent Watchdog reset flag.

+ Low-Power reset flag.

+ External Low Speed oscillator Bypass.

+ External Low Speed oscillator enable.

+ External Low Speed oscillator Ready.

+ LSE Ready Interrupt Clear.

+ LSE Ready Interrupt flag.

+ LSE Ready Interrupt Enable.

+ Internal Low Speed oscillator enable.

+ Internal Low Speed oscillator Ready.

+ LSI Ready Interrupt Clear.

+ LSI Ready Interrupt flag.

+ LSI Ready Interrupt Enable.

+ MCO[2:0] bits (Microcontroller Clock Output).

Bit 0.

Bit 1.

Bit 2.

HSE clock selected as MCO source.

HSI clock selected as MCO source.

No clock.

PLL clock divided by 2 selected as MCO source.

System clock selected as MCO source.

+ PIN reset flag.

+ PLLMUL[3:0] bits (PLL multiplication factor).

Bit 0.

Bit 1.

Bit 2.

Bit 3.

PLL input clock10.

PLL input clock*11.

PLL input clock*12.

PLL input clock*13.

PLL input clock*14.

PLL input clock*15.

PLL input clock*16.

PLL input clock*2.

PLL input clock*3.

PLL input clock*4.

PLL input clock*5.

PLL input clock*6.

PLL input clock*7.

PLL input clock*8.

PLL input clock*9.

+ PLL enable.

+ PLL clock ready flag.

+ PLL Ready Interrupt Clear.

+ PLL Ready Interrupt flag.

+ PLL Ready Interrupt Enable.

+ PLL entry clock source.

HSE clock selected as PLL entry clock source.

HSI clock divided by 2 selected as PLL entry clock source.

+ HSE divider for PLL entry.

HSE clock not divided for PLL entry.

HSE clock divided by 2 for PLL entry.

+ POR/PDR reset flag.

+ PRE1[2:0] bits (APB1 prescaler).

Bit 0.

Bit 1.

Bit 2.

HCLK not divided.

HCLK divided by 16.

HCLK divided by 2.

HCLK divided by 4.

HCLK divided by 8.

+ PRE2[2:0] bits (APB2 prescaler).

Bit 0.

Bit 1.

Bit 2.

HCLK not divided.

HCLK divided by 16.

HCLK divided by 2.

HCLK divided by 4.

HCLK divided by 8.

+ Power interface clock enable.

+ Power interface reset.

+ Remove reset flag.

+ RTC clock enable.

+ RTCSEL[1:0] bits (RTC clock source selection).

Bit 0.

Bit 1.

HSE oscillator clock divided by 128 used as RTC clock.

LSE oscillator clock used as RTC clock.

LSI oscillator clock used as RTC clock.

No clock.

+ SDIO clock enable.

+ Software Reset flag.

+ SPI 1 clock enable.

+ SPI 1 reset.

+ SPI 2 clock enable.

+ SPI 2 reset.

+ SPI 3 clock enable.

+ SPI 3 reset.

+ SRAM interface clock enable.

+ SW[1:0] bits (System clock Switch).

Bit 0.

Bit 1.

HSE selected as system clock.

HSI selected as system clock.

PLL selected as system clock.

+ SWS[1:0] bits (System Clock Switch Status).

Bit 0.

Bit 1.

HSE oscillator used as system clock.

HSI oscillator used as system clock.

PLL used as system clock.

+ TIM1 Timer clock enable.

+ TIM1 Timer reset.

+ Timer 2 clock enabled.

+ Timer 2 reset.

+ Timer 3 clock enable.

+ Timer 3 reset.

+ Timer 4 clock enable.

+ Timer 4 reset.

+ Timer 5 clock enable.

+ Timer 5 reset.

+ Timer 6 clock enable.

+ Timer 6 reset.

+ Timer 7 clock enable.

+ Timer 7 reset.

+ TIM8 Timer clock enable.

+ TIM8 Timer reset.

+ UART 4 clock enable.

+ UART 4 reset.

+ UART 5 clock enable.

+ UART 5 reset.

+ USART1 clock enable.

+ USART1 reset.

+ USART 2 clock enable.

+ USART 2 reset.

+ USART 3 clock enable.

+ USART 3 reset.

+ USB Device clock enable.

+ USB Device prescaler.

+ USB Device reset.

+ Window Watchdog clock enable.

+ Window Watchdog reset.

+ Window watchdog reset flag.

emgo:const.