+ ADC1 clock enable.

+ ADCPRE bit (ADC prescaler).

PCLK divided by 2.

PCLK divided by 4.

+ ADC reset.

+ Backup domain software reset.

+ CRC clock enable.

+ Clock Security System Interrupt Clear.

+ Clock Security System Interrupt flag.

+ Clock Security System enable.

+ DBGMCU clock enable.

+ DBGMCU reset.

+ DMA1 clock enable.

+ FLITF clock enable.

+ GPIOA clock enable.

+ GPIOA reset.

+ GPIOB clock enable.

+ GPIOB reset.

+ GPIOC clock enable.

+ GPIOC reset.

+ GPIOD clock enable.

+ GPIOD reset.

+ GPIOF clock enable.

+ GPIOF reset.

+ HPRE[3:0] bits (AHB prescaler).

SYSCLK not divided.

SYSCLK divided by 128.

SYSCLK divided by 16.

SYSCLK divided by 2.

SYSCLK divided by 256.

SYSCLK divided by 4.

SYSCLK divided by 512.

SYSCLK divided by 64.

SYSCLK divided by 8.

+ External High Speed clock Bypass.

+ External High Speed clock enable.

+ External High Speed clock ready flag.

+ HSE Ready Interrupt Clear.

+ HSE Ready Interrupt flag.

+ HSE Ready Interrupt Enable.

+ Internal High Speed 14MHz clock Calibration.

+ Internal High Speed 14MHz clock disable.

+ Internal High Speed 14MHz clock enable.

+ Internal High Speed 14MHz clock ready flag.

+ HSI14 Ready Interrupt Clear.

+ HSI14 Ready Interrupt flag.

+ HSI14 Ready Interrupt Enable.

+ Internal High Speed 14MHz clock trimming.

+ Internal High Speed clock Calibration.

+ Internal High Speed clock enable.

+ Internal High Speed clock ready flag.

+ HSI Ready Interrupt Clear.

+ HSI Ready Interrupt flag.

+ HSI Ready Interrupt Enable.

+ Internal High Speed clock trimming.

+ I2C1 clock enable.

+ I2C 1 reset.

+ I2C1SW bits.

HSI oscillator clock used as I2C1 clock source.

System clock selected as I2C1 clock source.

+ Independent Watchdog reset flag.

+ Low-Power reset flag.

+ External Low Speed oscillator Bypass.

+ LSEDRV[1:0] bits (LSE Osc.

+ External Low Speed oscillator enable.

+ External Low Speed oscillator Ready.

+ LSE Ready Interrupt Clear.

+ LSE Ready Interrupt flag.

+ LSE Ready Interrupt Enable.

+ Internal Low Speed oscillator enable.

+ Internal Low Speed oscillator Ready.

+ LSI Ready Interrupt Clear.

+ LSI Ready Interrupt flag.

+ LSI Ready Interrupt Enable.

+ MCO[3:0] bits (Microcontroller Clock Output).

HSE clock selected as MCO source.

HSI clock selected as MCO source.

HSI14 clock selected as MCO source.

LSE clock selected as MCO source.

LSI clock selected as MCO source.

No clock.

PLL clock divided by 2 selected as MCO source.

System clock selected as MCO source.

+ MCO prescaler.

MCO is divided by 1.

MCO is divided by 128.

MCO is divided by 16.

MCO is divided by 2.

MCO is divided by 32.

MCO is divided by 4.

MCO is divided by 64.

MCO is divided by 8.

+ OBL reset flag.

+ PIN reset flag.

+ PLLMUL[3:0] bits (PLL multiplication factor).

PLL input clock10.

PLL input clock*11.

PLL input clock*12.

PLL input clock*13.

PLL input clock*14.

PLL input clock*15.

PLL input clock*16.

PLL input clock*2.

PLL input clock*3.

PLL input clock*4.

PLL input clock*5.

PLL input clock*6.

PLL input clock*7.

PLL input clock*8.

PLL input clock*9.

+ PLL is not divided to MCO.

+ PLL enable.

+ PLL clock ready flag.

+ PLL Ready Interrupt Clear.

+ PLL Ready Interrupt flag.

+ PLL Ready Interrupt Enable.

+ PLL entry clock source.

HSE/PREDIV clock selected as PLL entry clock source.

HSI clock divided by 2 selected as PLL entry clock source.

+ HSE divider for PLL entry.

HSE/PREDIV clock not divided for PLL entry.

HSE/PREDIV clock divided by 2 for PLL entry.

+ POR/PDR reset flag.

+ PRE[2:0] bits (APB prescaler).

HCLK not divided.

HCLK divided by 16.

HCLK divided by 2.

HCLK divided by 4.

HCLK divided by 8.

+ PREDIV[3:0] bits.

PREDIV input clock not divided.

PREDIV input clock divided by 10.

PREDIV input clock divided by 11.

PREDIV input clock divided by 12.

PREDIV input clock divided by 13.

PREDIV input clock divided by 14.

PREDIV input clock divided by 15.

PREDIV input clock divided by 16.

PREDIV input clock divided by 2.

PREDIV input clock divided by 3.

PREDIV input clock divided by 4.

PREDIV input clock divided by 5.

PREDIV input clock divided by 6.

PREDIV input clock divided by 7.

PREDIV input clock divided by 8.

PREDIV input clock divided by 9.

+ PWR clock enable.

+ PWR reset.

+ Remove reset flag.

+ RTC clock enable.

+ RTCSEL[1:0] bits (RTC clock source selection).

HSE oscillator clock divided by 128 used as RTC clock.

LSE oscillator clock used as RTC clock.

LSI oscillator clock used as RTC clock.

No clock.

+ Software Reset flag.

+ SPI1 clock enable.

+ SPI1 reset.

+ SRAM interface clock enable.

+ SW[1:0] bits (System clock Switch).

HSE selected as system clock.

HSI selected as system clock.

PLL selected as system clock.

+ SWS[1:0] bits (System Clock Switch Status).

HSE oscillator used as system clock.

HSI oscillator used as system clock.

PLL used as system clock.

+ SYSCFG and comparator clock enable.

+ SYSCFG reset.

+ Timer 14 clock enable.

+ Timer 14 reset.

+ TIM16 clock enable.

+ TIM16 reset.

+ TIM17 clock enable.

+ TIM17 reset.

+ TIM1 clock enable.

+ TIM1 reset.

+ Timer 3 clock enable.

+ Timer 3 reset.

+ USART1 clock enable.

+ USART1 reset.

+ USART1SW[1:0] bits.

HSI oscillator clock used as USART1 clock source.

LSE oscillator clock used as USART1 clock source.

PCLK clock used as USART1 clock source.

System clock selected as USART1 clock source.

+ V1.8 power domain reset flag.

+ Window Watchdog clock enable.

+ Window Watchdog reset.

+ Window watchdog reset flag.

emgo:const.