package
0.0.0-20211205205814-168ccc21e67c
Repository: https://github.com/ziutek/emgo.git
Documentation: pkg.go.dev
# Constants
+ Auto-reload preload enable.
+ Break Generation.
+ Break interrupt enable.
+ Break interrupt Flag.
center-aligned mode 1: CCxF set when counting down,.
center-aligned mode 2: CCxF set when counting up,.
center-aligned mode 3: CCxF set on any direction.
Compare/capture channel numbers.
+ Capture/Compare 1 DMA request enable.
+ Capture/Compare 1 output enable.
+ Capture/Compare 1 Generation.
+ Capture/Compare 1 interrupt enable.
+ Capture/Compare 1 interrupt Flag.
+ Capture/Compare 1 Complementary output enable.
+ Capture/Compare 1 Complementary output Polarity.
+ Capture/Compare 1 Overcapture Flag.
as output,.
+ Capture/Compare 1 output Polarity.
+ Capture/Compare 1 Selection:.
input from TI1,.
input from TI2,.
input from TRC.
Compare/capture channel numbers.
+ Capture/Compare 2 DMA request enable.
+ Capture/Compare 2 output enable.
+ Capture/Compare 2 Generation.
+ Capture/Compare 2 interrupt enable.
+ Capture/Compare 2 interrupt Flag.
+ Capture/Compare 2 Complementary output enable.
+ Capture/Compare 2 Complementary output Polarity.
+ Capture/Compare 2 Overcapture Flag.
as output,.
+ Capture/Compare 2 output Polarity.
+ Capture/Compare 2 Selection:.
input from TI1,.
input from TI2,.
input from TRC.
Compare/capture channel numbers.
+ Capture/Compare 3 DMA request enable.
+ Capture/Compare 3 output enable.
+ Capture/Compare 3 Generation.
+ Capture/Compare 3 interrupt enable.
+ Capture/Compare 3 interrupt Flag.
+ Capture/Compare 3 Complementary output enable.
+ Capture/Compare 3 Complementary output Polarity.
+ Capture/Compare 3 Overcapture Flag.
as output,.
+ Capture/Compare 3 output Polarity.
+ Capture/Compare 3 Selection:.
input from TI3,.
input from TI4,.
input from TRC.
Compare/capture channel numbers.
+ Capture/Compare 4 DMA request enable.
+ Capture/Compare 4 output enable.
+ Capture/Compare 4 Generation.
+ Capture/Compare 4 interrupt enable.
+ Capture/Compare 4 interrupt Flag.
+ Capture/Compare 4 Complementary output Polarity.
+ Capture/Compare 4 Overcapture Flag.
as output,.
+ Capture/Compare 4 output Polarity.
+ Capture/Compare 4 Selection:.
input from TI3,.
input from TI4,.
input from TRC.
+ Capture/Compare DMA Selection.
+ Capture/Compare Preloaded Control.
+ Capture/Compare Control Update Selection.
+ Counter enable.
+ Clock division (used by digital filters):.
t_DTS = t_CK_INT,.
t_DTS = 2*t_CK_INT,.
t_DTS = 4*t_CK_INT.
+ Center-aligned mode selection:.
+ COM DMA request enable.
+ Capture/Compare Control Update Generation.
+ COM interrupt enable.
+ COM interrupt Flag.
+ Counter direction: 0: up (CNT+), 1: down (CNT-).
edge-aligned mode (DIR sets direction),.
+ External clock enable.
+ External trigg.
+ External trigger polarity.
+ External trigger prescaler:.
prescaller off,.
ETRP /= 2,.
ETRP /= 4,.
ETRP /= 8.
external trigger input.
f_SAMPLING = f_CK_INT, N = 2.
f_SAMPLING = f_CK_INT, N = 4.
f_SAMPLING = f_CK_INT, N = 8.
f_SAMPLING = f_DTS/16, N = 5.
f_SAMPLING = f_DTS/16, N = 6.
f_SAMPLING = f_DTS/16, N = 8.
f_SAMPLING = f_DTS/2, N = 6.
f_SAMPLING = f_DTS/2, N = 8.
f_SAMPLING = f_DTS/32, N = 5.
f_SAMPLING = f_DTS/32, N = 6.
f_SAMPLING = f_DTS/32, N = 8.
f_SAMPLING = f_DTS/4, N = 6.
f_SAMPLING = f_DTS/4, N = 8.
f_SAMPLING = f_DTS/8, N = 6.
f_SAMPLING = f_DTS/8, N = 8.
No filter, sampling at f_DTS.
+ Input Capture 1 Filter.
+ Input Capture 1 Prescaler:.
+ Input Capture 2 Filter.
+ Input Capture 2 Prescaler:.
+ Input Capture 3 Filter.
+ Input Capture 3 Prescaler.
+ Input Capture 4 Filter.
+ Input Capture 4 Prescaler.
No prescaler.
Capture once every 2 events.
Capture once every 4 events.
Capture once every 8 events.
internal trigger 0,.
internal trigger 1,.
internal trigger 2,.
internal trigger 3,.
SR.CC1IF (enven if not cleared),.
CNT_EN = CR1.CEN | TRGI,.
OC1REF,.
OC2REF,.
OC3REF,.
OC4REF.
+ Master Mode Selection (what is used as TRGO):.
EGR.UG bit,.
update event,.
+ Master/slave mode.
+ Output Compare 1 Clear Enable.
+ Output Compare 1 Fast enable.
+ Output Compare 1 Mode.
+ Output Compare 1 Preload enable.
+ Output Compare 2 Clear Enable.
+ Output Compare 2 Fast enable.
+ Output Compare 2 Mode.
+ Output Compare 2 Preload enable.
+ Output Compare 3 Clear Enable.
+ Output Compare 3 Fast enable.
+ Output Compare 3 Mode.
+ Output Compare 3 Preload enable.
+ Output Compare 4 Clear Enable.
+ Output Compare 4 Fast enable.
+ Output Compare 4 Mode.
+ Output Compare 4 Preload enable.
OCxREF is frozen.
OCxREF forced high.
OCxREF set to high on match.
OCxREF set to low on match.
OCxREF forced low.
PWM mode 1: OCxREF = CNT+ < CCR1, CNT- ≤ CCR1.
PWM mode 2: OCxREF = CNT+ ≥ CCR1, CNT- > CCR1.
OCxREF toggles on match.
+ Output Idle state 1 (OC1 output).
+ Output Idle state 1 (OC1N output).
+ Output Idle state 2 (OC2 output).
+ Output Idle state 2 (OC2N output).
+ Output Idle state 3 (OC3 output).
+ Output Idle state 3 (OC3N output).
+ Output Idle state 4 (OC4 output).
+ One pulse mode.
slave mode disabled,.
encoder mode 1: counts on TI2FP2 edge,.
encoder mode 2: counts on TI1FP1 edge,.
encoder mode 3: counts on TI1FP1, TI2FP2 edge.
rxternal clock mode: TRGI clocks the counter.
gated mode: TRGI high enables counter clock,.
reset mode: TRGI reinitializes the counter,.
+ Slave mode selection:.
trigger mode: TRGI starts the counter,.
+ Trigger DMA request enable.
+ Trigger Generation.
TI1 edge detector,.
filtered timer input 1,.
filtered timer input 2,.
+ TI1 Selection.
+ Trigger interrupt enable.
+ Trigger interrupt Flag.
+ Trigger selection (what is used as TRGI):.
+ Update DMA request enable.
+ Update disable.
+ Update Generation.
+ Update interrupt enable.
+ Update interrupt Flag.
+ Update request source.