modulepackage
0.0.0-20240502050841-c90245dc26ed
Repository: https://github.com/wasilibs/go-capstone.git
Documentation: pkg.go.dev
# README
go-capstone
Simple wazero wrapper around capstone, currently only to assist wazero development. If there is demand for properly exposing the library, we can add more API and release officially.
# Packages
No description provided by the author
# Functions
No description provided by the author
# Constants
< AArch64.
All architectures - for cs_support().
< Alpha architecture.
< ARM architecture (including Thumb, Thumb-2).
< Berkeley Packet Filter architecture (including eBPF).
< Ethereum architecture.
< 680X architecture.
< 68K architecture.
No description provided by the author
< Mips architectureq.
< MOS65XX architecture (including MOS6502).
< PowerPC architecture.
< RISCV architecture.
< SH architecture.
< Sparc architecture.
< SystemZ architecture.
< TMS320C64x architecture.
< TriCore architecture.
< WebAssembly architecture.
< X86 architecture (including x86 & x86-64).
< XCore architecture.
< 16-bit mode (X86).
< 32-bit mode (X86).
< 64-bit mode (X86, PPC).
< 32-bit ARM.
< big-endian mode.
< Book-E mode (PPC).
< Classic BPF mode (default).
< Extended BPF mode.
< little-endian mode (default mode).
< M680X Hitachi 6301,6303 mode.
< M680X Hitachi 6309 mode.
< M680X Motorola 6800,6802 mode.
< M680X Motorola 6801,6803 mode.
< M680X Motorola/Freescale 6805 mode.
< M680X Motorola/Freescale/NXP 68HC08 mode.
< M680X Motorola 6809 mode.
< M680X Motorola/Freescale/NXP 68HC11 mode.
< M680X Motorola/Freescale/NXP CPU12.
< M680X Freescale/NXP HCS08 mode.
< M68K 68000 mode.
< M68K 68010 mode.
< M68K 68020 mode.
< M68K 68030 mode.
< M68K 68040 mode.
< M68K 68060 mode.
< ARM's Cortex-M series.
< MicroMips mode (MIPS).
< Mips II ISA.
< Mips III ISA.
< Mips32 ISA (Mips).
< Mips32r6 ISA.
< Mips64 ISA (Mips).
< MOS65XXX MOS 6502.
< MOS65XXX WDC 65816, 8-bit m/x.
< MOS65XXX WDC 65816, 16-bit m, 8-bit x.
No description provided by the author
< MOS65XXX WDC 65816, 8-bit m, 16-bit x.
< MOS65XXX WDC 65c02.
< MOS65XXX WDC W65c02.
< Paired-singles mode (PPC).
< Quad Processing eXtensions mode (PPC).
< RISCV RV32G.
< RISCV RV64G.
< RISCV compressed instructure mode.
< SH2.
< SH2A.
< SH3.
< SH4.
< SH4A.
< w/ DSP.
< w/ FPU.
< Signal Processing Engine mode (PPC).
< ARM's Thumb mode, including Thumb-2.
< Tricore 1.1.
< Tricore 1.2.
< Tricore 1.3.
< Tricore 1.3.1.
< Tricore 1.6.
< Tricore 1.6.1.
< Tricore 1.6.2.
< ARMv8 A32 encodings for ARM.
< SparcV9 mode (Sparc).
< Break down instruction structure into details.
< If enabled, always sets the real instruction detail.
< No option specified.
< User-defined dynamic memory related functions.
< Customize instruction mnemonic.
< Change engine's mode at run-time.
< ARM, prints branch immediates without offset.
< Turn OFF an option - default for OPT_DETAIL, OPT_SKIPDATA, OPT_UNSIGNED.
< Turn ON an option (OPT_DETAIL, OPT_SKIPDATA).
< Skip data when disassembling.
< Setup user-defined function for SKIPDATA option.
< Assembly output syntax.
< X86 ATT asm syntax (OPT_SYNTAX).
< Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.).
< Default asm syntax (OPT_SYNTAX).
< X86 Intel asm syntax - default on X86 (OPT_SYNTAX).
< X86 Intel Masm syntax (OPT_SYNTAX).
< MOS65XX use $ as hex prefix.
< Prints register name with only number (OPT_SYNTAX).
< Prints the % in front of PPC registers.
< print immediate operands in unsigned form.