# Functions
Run the given assembly code.
Run the given inline assembly.
DisableInterrupts disables all interrupts, and returns the old interrupt state.
EnableInterrupts enables all interrupts again.
# Constants
Cycle counter for RDCYCLE instruction.
Upper 32 bits of CYCLE, RV32I only.
Debug control and status register.
Debug PC.
Debug scratch register.
Floating-Point Control and Status.
Floating-Point Accrued Exceptions.
Floating-Point Dynamic Rounding Mode.
Performance-monitoring counter 10.
Upper 32 bits of HPMCOUNTER10, RV32I only.
Performance-monitoring counter 11.
Upper 32 bits of HPMCOUNTER11, RV32I only.
Performance-monitoring counter 12.
Upper 32 bits of HPMCOUNTER12, RV32I only.
Performance-monitoring counter 13.
Upper 32 bits of HPMCOUNTER13, RV32I only.
Performance-monitoring counter 14.
Upper 32 bits of HPMCOUNTER14, RV32I only.
Performance-monitoring counter 15.
Upper 32 bits of HPMCOUNTER15, RV32I only.
Performance-monitoring counter 16.
Upper 32 bits of HPMCOUNTER16, RV32I only.
Performance-monitoring counter 17.
Upper 32 bits of HPMCOUNTER17, RV32I only.
Performance-monitoring counter 18.
Upper 32 bits of HPMCOUNTER18, RV32I only.
Performance-monitoring counter 19.
Upper 32 bits of HPMCOUNTER19, RV32I only.
Performance-monitoring counter 20.
Upper 32 bits of HPMCOUNTER20, RV32I only.
Performance-monitoring counter 21.
Upper 32 bits of HPMCOUNTER21, RV32I only.
Performance-monitoring counter 22.
Upper 32 bits of HPMCOUNTER22, RV32I only.
Performance-monitoring counter 23.
Upper 32 bits of HPMCOUNTER23, RV32I only.
Performance-monitoring counter 24.
Upper 32 bits of HPMCOUNTER24, RV32I only.
Performance-monitoring counter 25.
Upper 32 bits of HPMCOUNTER25, RV32I only.
Performance-monitoring counter 26.
Upper 32 bits of HPMCOUNTER26, RV32I only.
Performance-monitoring counter 27.
Upper 32 bits of HPMCOUNTER27, RV32I only.
Performance-monitoring counter 28.
Upper 32 bits of HPMCOUNTER28, RV32I only.
Performance-monitoring counter 29.
Upper 32 bits of HPMCOUNTER29, RV32I only.
Performance-monitoring counter 3.
Performance-monitoring counter 30.
Upper 32 bits of HPMCOUNTER30, RV32I only.
Performance-monitoring counter 31.
Upper 32 bits of HPMCOUNTER31, RV32I only.
Upper 32 bits of HPMCOUNTER3, RV32I only.
Performance-monitoring counter 4.
Upper 32 bits of HPMCOUNTER4, RV32I only.
Performance-monitoring counter 5.
Upper 32 bits of HPMCOUNTER5, RV32I only.
Performance-monitoring counter 6.
Upper 32 bits of HPMCOUNTER6, RV32I only.
Performance-monitoring counter 7.
Upper 32 bits of HPMCOUNTER7, RV32I only.
Performance-monitoring counter 8.
Upper 32 bits of HPMCOUNTER8, RV32I only.
Performance-monitoring counter 9.
Upper 32 bits of HPMCOUNTER9, RV32I only.
Instructions-retired counter for RDINSTRET instruction.
Upper 32 bits of INSTRET, RV32I only.
Architecture ID.
Machine trap cause.
Machine counter enable.
Upper 32 bits of MCYCLE, RV32I only.
Machine exception delegation register.
Machine exception program counter.
Hardware thread ID.
Machine performance-monitoring counter 10.
Upper 32 bits of MHPMCOUNTER10, RV32I only.
Machine performance-monitoring counter 11.
Upper 32 bits of MHPMCOUNTER11, RV32I only.
Machine performance-monitoring counter 12.
Upper 32 bits of MHPMCOUNTER12, RV32I only.
Machine performance-monitoring counter 13.
Upper 32 bits of MHPMCOUNTER13, RV32I only.
Machine performance-monitoring counter 14.
Upper 32 bits of MHPMCOUNTER14, RV32I only.
Machine performance-monitoring counter 15.
Upper 32 bits of MHPMCOUNTER15, RV32I only.
Machine performance-monitoring counter 16.
Upper 32 bits of MHPMCOUNTER16, RV32I only.
Machine performance-monitoring counter 17.
Upper 32 bits of MHPMCOUNTER17, RV32I only.
Machine performance-monitoring counter 18.
Upper 32 bits of MHPMCOUNTER18, RV32I only.
Machine performance-monitoring counter 19.
Upper 32 bits of MHPMCOUNTER19, RV32I only.
Machine performance-monitoring counter 20.
Upper 32 bits of MHPMCOUNTER20, RV32I only.
Machine performance-monitoring counter 21.
Upper 32 bits of MHPMCOUNTER21, RV32I only.
Machine performance-monitoring counter 22.
Upper 32 bits of MHPMCOUNTER22, RV32I only.
Machine performance-monitoring counter 23.
Upper 32 bits of MHPMCOUNTER23, RV32I only.
Machine performance-monitoring counter 24.
Upper 32 bits of MHPMCOUNTER24, RV32I only.
Machine performance-monitoring counter 25.
Upper 32 bits of MHPMCOUNTER25, RV32I only.
Machine performance-monitoring counter 26.
Upper 32 bits of MHPMCOUNTER26, RV32I only.
Machine performance-monitoring counter 27.
Upper 32 bits of MHPMCOUNTER27, RV32I only.
Machine performance-monitoring counter 28.
Upper 32 bits of MHPMCOUNTER28, RV32I only.
Machine performance-monitoring counter 29.
Upper 32 bits of MHPMCOUNTER29, RV32I only.
Machine performance-monitoring counter 3.
Machine performance-monitoring counter 30.
Upper 32 bits of MHPMCOUNTER30, RV32I only.
Machine performance-monitoring counter 31.
Upper 32 bits of MHPMCOUNTER31, RV32I only.
Upper 32 bits of MHPMCOUNTER3, RV32I only.
Machine performance-monitoring counter 4.
Upper 32 bits of MHPMCOUNTER4, RV32I only.
Machine performance-monitoring counter 5.
Upper 32 bits of MHPMCOUNTER5, RV32I only.
Machine performance-monitoring counter 6.
Upper 32 bits of MHPMCOUNTER6, RV32I only.
Machine performance-monitoring counter 7.
Upper 32 bits of MHPMCOUNTER7, RV32I only.
Machine performance-monitoring counter 8.
Upper 32 bits of MHPMCOUNTER8, RV32I only.
Machine performance-monitoring counter 9.
Upper 32 bits of MHPMCOUNTER9, RV32I only.
Machine performance-monitoring event selector 10.
Machine performance-monitoring event selector 11.
Machine performance-monitoring event selector 12.
Machine performance-monitoring event selector 13.
Machine performance-monitoring event selector 14.
Machine performance-monitoring event selector 15.
Machine performance-monitoring event selector 16.
Machine performance-monitoring event selector 17.
Machine performance-monitoring event selector 18.
Machine performance-monitoring event selector 19.
Machine performance-monitoring event selector 20.
Machine performance-monitoring event selector 21.
Machine performance-monitoring event selector 22.
Machine performance-monitoring event selector 23.
Machine performance-monitoring event selector 24.
Machine performance-monitoring event selector 25.
Machine performance-monitoring event selector 26.
Machine performance-monitoring event selector 27.
Machine performance-monitoring event selector 28.
Machine performance-monitoring event selector 29.
Machine performance-monitoring event selector 30.
Machine performance-monitoring event selector 31.
Machine performance-monitoring event selector 4.
Machine performance-monitoring event selector 5.
Machine performance-monitoring event selector 6.
Machine performance-monitoring event selector 7.
Machine performance-monitoring event selector 8.
Machine performance-monitoring event selector 9.
Machine interrupt delegation register.
Machine interrupt-enable register.
Implementation ID.
Upper 32 bits of MINSTRET, RV32I only.
Machine interrupt pending.
ISA and extensions.
Scratch register for machine trap handlers.
Machine status register.
Machine bad address or instruction.
Machine trap-handler base address.
Vendor ID.
Physical memory protection address register 0.
Physical memory protection address register 1.
Physical memory protection address register 10.
Physical memory protection address register 11.
Physical memory protection address register 12.
Physical memory protection address register 13.
Physical memory protection address register 14.
Physical memory protection address register 15.
Physical memory protection address register 2.
Physical memory protection address register 3.
Physical memory protection address register 4.
Physical memory protection address register 5.
Physical memory protection address register 6.
Physical memory protection address register 7.
Physical memory protection address register 8.
Physical memory protection address register 9.
Physical memory protection configuration.
Physical memory protection configuration, RV32 only.
Physical memory protection configuration.
Physical memory protection configuration, RV32 only.
Supervisor address translation and protection.
Supervisor trap cause.
Supervisor counter enable.
Supervisor exception delegation register.
Supervisor exception program counter.
Supervisor interrupt delegation register.
Supervisor interrupt-enable register.
Supervisor interrupt pending.
Scratch register for supervisor trap handlers.
Supervisor status register.
Supervisor bad address or instruction.
Supervisor trap handler base address.
First Debug/Trace trigger data register.
Second Debug/Trace trigger data register.
Third Debug/Trace trigger data register.
Timer for RDTIME instruction.
Upper 32 bits of TIME, RV32I only.
Debug/Trace trigger register select.
User trap cause.
User exception program counter.
User interrupt-enable register.
User interrupt pending.
Scratch register for user trap handlers.
User status register.
User bad address or instruction.
User trap handler base address.
# Type aliases
CSR constants are used for use in CSR (Control and Status Register) compiler intrinsics.