AES hardware implementation.

Advanced SIMD (always available).

Advanced SIMD double precision instruction set.

Advanced SIMD multiplication FP16 to FP32.

Advanced SIMD half precision instruction set.

Rounding double multiply add/subtract instruction set.

Atomic memory operation instruction set.

CPUID identification scheme registers.

CRC32 hardware implementation.

Persistent memory support.

Event stream support.

Floating-point multiplication and addition of complex numbers.

Floating-point instruction set (always available).

Half precision floating-point instruction set.

Javascript conversion from floating-point to integer.

Release Consistent processor consistent support.

Polynomial multiplication instruction set.

SHA1 hardware implementation.

SHA2 hardware implementation.

SHA3 hardware implementation.

SHA512 hardware implementation.

SM3 hardware implementation.

SM4 hardware implementation.

Scalable Vector Extensions.