* Rx DCA Control Register: * 00-15 : 0x02200 + n*4 * 16-64 : 0x0100C + n*0x40 * 64-127: 0x0D00C + (n-64)*0x40 */.

Recieve DMA RegistersTodo: Copypaste für den Rest.

8 of these 0x03C00 - 0x03C1C */.

* Split and Replication Receive Control Registers * 00-15 : 0x02100 + n*4 * 16-64 : 0x01014 + n*0x40 * 64-127: 0x0D014 + (n-64)*0x40 */.

IxyInit initializes the driver and hands back the interface.

IxyTxBatchBusyWait calls dev.TxBatch until all packets are queued with busy waiting.

MemoryAllocateMempool allocate mempool with numEntries*entrySizeallocate a memory pool from which DMA'able packet buffers can be allocatedthis is currently not yet thread-safe, i.e., a pool can only be used by one thread,this means a packet can only be sent/received by a single threadentry_size can be 0 to use the default.

PktBufAlloc allocates a single packet in the mempool.

PktBufAllocBatch allocates a batch of packets in the mempool, use PktBufAlloc for single packets.

PktBufFree frees PktBuf.

Check Context */.

DDP hdr type or iSCSI */.

Desc ext 1=Adv */.

End of Packet */.

Insert FCS */.

Report Status */.

TCP Seg enable */.

VLAN pkt enable */.

Data buf length(bytes) */.

Adv Context Desc */.

Adv Data Descriptor */.

DTYP mask */.

11: EOFa */.

FC EOF index */.

00: EOFn */.

10: EOFni */.

01: EOFt */.

Orientation End */.

Orientation Start */.

Rel_Off in F_CTL */.

FC SOF index */.

Adv desc Index shift */.

IPSec ESP length */.

IPSec SA index */.

Adv ctxt L4LEN shift */.

Insert LinkSec */.

IEEE1588 time stamp */.

Adv ctxt desc mac len shift */.

Adv ctxt MSS shift */.

Adv ctxt OUTERIPLEN shift */.

Adv Tx Desc OUTERIPCS Shift */.

Adv Tx Desc OUTERIPCS Shift for X550EM_a */.

Adv desc PAYLEN shift */.

IPSec offload request */.

1st TSO of iSCSI PDU */.

1st&Last TSO-full iSCSI PDU */.

Last TSO of iSCSI PDU */.

Middle TSO of iSCSI PDU */.

Adv Transmit Descriptor Config Masks */.

POPTS Reserved */.

Adv desc POPTS shift */.

Adv Transmit Descriptor Config Masks */.

Descriptor Done */.

STA Reserved */.

NXTSEQ/SEED pres in WB */.

ESP Encrypt Enable */.

IPSec Type ESP */.

IP Packet Type: 1=IPv4 */.

IP Packet Type: 0=IPv6 */.

RSV L4 Packet TYPE */.

L4 Packet TYPE of SCTP */.

L4 Packet TYPE of TCP */.

L4 Packet TYPE of UDP */.

req Markers and CRC */.

Adv ctxt TUNNELLEN shift */.

Adv Tx Desc Tunnel Type NVGRE */.

Adv Tx Desc Tunnel Type shift */.

Adv ctxt vlan tag shift */.

FCoE Frame Type */.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

4.5 Seconds */.

MAC Registers.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

MAC Registers.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

AUTOC Bit Masks */.

MAC Registers.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Driver loaded bit for FW */.

No Snoop disable */.

Physical Function Reset Done */.

Relaxed Ordering disable */.

Global IO Master Disable bit */.

Link Reset.

Reset (SW) */.

CTRL Bit Masks */.

Global Double VLAN */.

Bit 6 */.

Bit 5 */.

No Snoop LSO hdr buffer */.

Transmit Enable */.

VLAN EtherType */.

Transmit DMA registers */.

EEPROM Auto Read Done */.

EEPROM Chip Select */.

EEPROM Data In */.

EEPROM Data Out */.

Flash update done */.

Flash update command */.

Disable FLASH writes */.

Enable FLASH writes */.

FLASH Write Enable */.

EEC Register */.

EEPROM Access Grant */.

EEPROM Present */.

EEPROM Access Request */.

Sector 1 Valid */.

EEPROM Clock */.

Interrupt Registers */.

Interrupt Registers */.

Interrupt Registers */.

Interrupt Registers */.

Interrupt Registers */.

Interrupt Registers */.

Stats registers */.

Num of Good Eth CRC w/ Bad FC CRC */.

CRC_CNT: bit 0 - 15 */.

FCoE Last Error Count */.

Last_CNT: bit 0 - 15 */.

Number of FCoE DWords Received */.

Number of FCoE DWords Transmitted */.

Number of FCoE Packets Received */.

Number of FCoE Packets Transmitted */.

FCoE Rx Packets Dropped Count */.

Broadcast Accept Mode */.

Discard Pause Frame */.

Multicast Promiscuous Ena*/.

Pass MAC Control Frames */.

Receive Flow Control Ena */.

Receive Priority Flow Control Enable */.

Store Bad Packet */.

Unicast Promiscuous Ena */.

MAC Registers.

MAC Registers.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

MAC Registers.

bit 17 */.

bit 18 */.

bit 2 */.

bit 15 */.

bit 16 */.

bits 20-23 */.

bit 24 */.

bit 1 */.

bit 27 */.

bit 28 */.

bit 14 */.

bits 25-26 */.

bit 0 */.

bit 10 */.

bit 12 */.

MAC Registers.

Stats registers */.

MAC Registers.

MAC Registers.

Adv Transmit Descriptor Config Masks */.

Adv Transmit Descriptor Config Masks */.

Adv Transmit Descriptor Config Masks */.

Adv Transmit Descriptor Config Masks */.

Adv Transmit Descriptor Config Masks */.

Adv Transmit Descriptor Config Masks */.

Adv Transmit Descriptor Config Masks */.

Adv Transmit Descriptor Config Masks */.

Adv Transmit Descriptor Config Masks */.

9.0 Seconds */.

MAC Registers.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

LINKS Bit Masks */.

MAC Registers.

LINKS Bit Masks */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

Packet Buffer Initialization */.

Packet Buffer Initialization */.

MAC Registers.

MAC Registers.

Discard Pause Frame */.

Pass MAC Control Frames */.

Receive FC Enable */.

Receive Priority FC Enable */.

Rx Priority FC bitmap mask */.

Rx Priority FC bitmap shift */.

MAC Registers.

MAC Registers.

Stats registers */.

MAC Registers.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

MAC Registers.

Stats registers */.

MAC Registers.

Stats registers */.

MAC Registers.

Stats registers */.

Stats registers */.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

MAC Registers.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Aggregation disable */.

CRC Strip */.

DMA init cycle done */.

must set 1 when RSC ena */.

RDRXCTL Bit Masks */.

RDRXCTL Bit Masks */.

RDRXCTL Bit Masks */.

Pad Small Packet */.

Rx Desc Min THLD Size */.

RDRXCTL Bit Masks */.

RDRXCTL Bit Masks */.

must set 1 when RSC ena */.

RSC First packet size */.

Disable RSC compl on LLI*/.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

BCN (for DCB) Registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB arbiter disable */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

DCB registers */.

Stats registers */.

Receive Registers */.

Desc Monitor Bypass */.

Enable Receiver */.

CFI is bit 12 */.

Receive Descriptor bit definitions */.

CRC Error */.

IP Checksum Error */.

Length Error */.

Oversize Error */.

Packet Error */.

TCP/UDP Checksum Error */.

Undersize Error */.

Priority is in upper 3 bits */.

Receive Descriptor bit definitions */.

ACK Packet indication */.

Speculative CRC Valid */.

Descriptor Done */.

Pkt caused INT via DYNINT */.

End of Packet */.

FDir Match */.

IP xsum calculated */.

L4 xsum calculated */.

Loopback Status */.

Pkt caused Low Latency Interrupt */.

Cloud IP xsum calculated */.

passed in-exact filter */.

Security Processing */.

Time Stamp */.

Time Stamp in packet buffer */.

UDP xsum calculated */.

Valid UDP checksum */.

1st VLAN found */.

IEEE VLAN Packet */.

VLAN ID is in lower 12 bits */.

CRC Error */.

FCEOFe/IPE */.

FCERR/FDIRERR */.

FDIR Collision error */.

FDIR Drop error */.

FDIR Length error */.

Header Buffer Overflow */.

IP Checksum Error */.

Length Error */.

RDESC.ERRORS mask */.

Oversize Error */.

CRC IP Header error */.

Packet Error */.

Any MAC Error */.

RDESC.ERRORS shift */.

TCP/UDP Checksum Error */.

Undersize Error */.

Next Descriptor Index */.

Receive Descriptor bit definitions */.

Done */.

End of Packet */.

FCoE EOF/SOF Stat */.

FCoE Pkt Stat */.

11: Ctxt w/ DDP */.

10: Recv.

01: Ctxt w/o DDP */.

00: No Ctxt Match */.

FDir Match */.

Stat/NEXTP: bit 0-19 */.

IEEE1588 Time Stamp */.

Time Stamp in packet buffer */.

IEEE VLAN Pkt */.

Ena specific Rx Queue */.

Receive Config masks */.

X540 supported only */.

Rx Desc wr-bk flushing */.

VLAN mode enable */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

128KB Packet Buffer */.

48KB Packet Buffer */.

64KB Packet Buffer */.

80KB Packet Buffer */.

512KB Packet Buffer */.

MAC Registers.

MAC Registers.

MAC Registers.

SRRCTL bit definitions */.

64byte resolution (>> 6) + at bit 8 offset (<< 8) = (<< 2) */.

SRRCTL bit definitions */.

so many KBs */.

SRRCTL bit definitions */.

SRRCTL bit definitions */.

SRRCTL bit definitions */.

SRRCTL bit definitions */.

SRRCTL bit definitions */.

SRRCTL bit definitions */.

SRRCTL bit definitions */.

SRRCTL bit definitions */.

SRRCTL bit definitions */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

Stats registers */.

MAC Registers.

Desc extension (0 = legacy) */.

End of Packet */.

Insert Checksum */.

Insert FCS (Ethernet CRC) */.

Report Status */.

Add VLAN tag */.

Insert IP checksum */.

Insert TCP/UDP checksum */.

Descriptor Done */.

Ena specific Tx Queue */.

Tx Desc.

shift to WTHRESH bits */.

Statistics Registers */.

Statistics Registers */.

Statistics Registers */.

20KB Packet Buffer */.

40KB Packet Buffer */.

160KB Packet Buffer */.

Max Tx Packet size */.

Stats registers */.

MAC Registers.

DeviceStats holds stats.

Receive Descriptor - Advanced */union ixgbe_adv_rx_desc { struct { __le64 pkt_addr; //Packet buffer address __le64 hdr_addr; //Header buffer address } read; struct { struct { union { __le32 data; struct { __le16 pkt_info; //RSS, Pkt type __le16 hdr_info; //Splithdr, hdrlen } hs_rss; } lo_dword; union { __le32 rss; //RSS Hash struct { __le16 ip_id; //IP id __le16 csum; //Packet Checksum } csum_ip; } hi_dword; } lower; struct { __le32 status_error; //ext status/error __le16 length; //Packet length __le16 vlan; //VLAN tag } upper; } wb; writeback };*/.

Transmit Descriptor - Advanced */union ixgbe_adv_tx_desc { struct { __le64 buffer_addr; // Address of descriptor's data buf __le32 cmd_type_len; __le32 olinfo_status; } read; struct { __le64 rsvd; // Reserved __le32 nxtseq_seed; __le32 status; } wb; };*/.

IxyDevice contains information common across all substrates.

IxyDummy is a dummy implementation for testing purposes.

IxyError represents an error with the ixy device.

Mempool struct that describes a mempool.

PktBuf bundles the raw byte representation of a buffer with the corresponding mempool.

IxyInterface is the interface that has to be implemented for all substrates such as the ixgbe or virtio.