pkg.gl

Categorygithub.com/go-lpc/mimedainternalregs

package

0.7.0

Repository: https://github.com/go-lpc/mim.git

Documentation: pkg.go.dev

# Constants

ALT_LWFPGASLVS_OFST

No description provided by the author

ALTERA_AVALON_FIFO_ALMOSTEMPTY_REG

No description provided by the author

ALTERA_AVALON_FIFO_ALMOSTFULL_REG

No description provided by the author

ALTERA_AVALON_FIFO_DATA_REG

No description provided by the author

ALTERA_AVALON_FIFO_EVENT_ALL

No description provided by the author

ALTERA_AVALON_FIFO_EVENT_REG

No description provided by the author

ALTERA_AVALON_FIFO_IENABLE_AE_MSK

No description provided by the author

ALTERA_AVALON_FIFO_IENABLE_AF_MSK

No description provided by the author

ALTERA_AVALON_FIFO_IENABLE_ALL

No description provided by the author

ALTERA_AVALON_FIFO_IENABLE_E_MSK

No description provided by the author

ALTERA_AVALON_FIFO_IENABLE_F_MSK

No description provided by the author

ALTERA_AVALON_FIFO_IENABLE_OVF_MSK

No description provided by the author

ALTERA_AVALON_FIFO_IENABLE_REG

No description provided by the author

ALTERA_AVALON_FIFO_IENABLE_UDF_MSK

No description provided by the author

ALTERA_AVALON_FIFO_LEVEL_REG

No description provided by the author

ALTERA_AVALON_FIFO_OTHER_INFO_REG

No description provided by the author

ALTERA_AVALON_FIFO_STATUS_AE_MSK

No description provided by the author

ALTERA_AVALON_FIFO_STATUS_AF_MSK

No description provided by the author

ALTERA_AVALON_FIFO_STATUS_ALL

No description provided by the author

ALTERA_AVALON_FIFO_STATUS_E_MSK

No description provided by the author

ALTERA_AVALON_FIFO_STATUS_F_MSK

No description provided by the author

ALTERA_AVALON_FIFO_STATUS_OVF_MSK

No description provided by the author

ALTERA_AVALON_FIFO_STATUS_REG

No description provided by the author

ALTERA_AVALON_FIFO_STATUS_UDF_MSK

No description provided by the author

CMD_DIGITAL_RO

No description provided by the author

CMD_IDLE

No description provided by the author

CMD_RAMFULL_EXT

No description provided by the author

CMD_RESET_BCID

commands.

CMD_START_ACQ

No description provided by the author

CMD_STOP_ACQ

No description provided by the author

EDA_DIF_ID_OFFS

No description provided by the author

H2F_BASE

setting for the HPS to FPGA AXI Bridge.

H2F_FIFO_DAQ_CSR_RFM0

No description provided by the author

H2F_FIFO_DAQ_CSR_RFM1

No description provided by the author

H2F_FIFO_DAQ_CSR_RFM2

No description provided by the author

H2F_FIFO_DAQ_CSR_RFM3

No description provided by the author

H2F_FIFO_DAQ_RFM0

slave addresses (prefixed by the bridge used) see ../FPGA_SoC/soc_system/soc_system.html.

H2F_FIFO_DAQ_RFM1

No description provided by the author

H2F_FIFO_DAQ_RFM2

No description provided by the author

H2F_FIFO_DAQ_RFM3

No description provided by the author

H2F_MASK

No description provided by the author

H2F_SPAN

enough.

LW_H2F_BASE

settings for the lightweight HPS to FPGA bridge.

LW_H2F_BUTTON_PIO

No description provided by the author

LW_H2F_LED_PIO

No description provided by the author

LW_H2F_MASK

No description provided by the author

LW_H2F_PIO_CNT_HIT0_RFM0

No description provided by the author

LW_H2F_PIO_CNT_HIT0_RFM1

No description provided by the author

LW_H2F_PIO_CNT_HIT0_RFM2

No description provided by the author

LW_H2F_PIO_CNT_HIT0_RFM3

No description provided by the author

LW_H2F_PIO_CNT_HIT1_RFM0

No description provided by the author

LW_H2F_PIO_CNT_HIT1_RFM1

No description provided by the author

LW_H2F_PIO_CNT_HIT1_RFM2

No description provided by the author

LW_H2F_PIO_CNT_HIT1_RFM3

No description provided by the author

LW_H2F_PIO_CNT_TRIG

No description provided by the author

LW_H2F_PIO_CNT24

No description provided by the author

LW_H2F_PIO_CNT48_LSB

No description provided by the author

LW_H2F_PIO_CNT48_MSB

No description provided by the author

LW_H2F_PIO_CTRL_OUT

No description provided by the author

LW_H2F_PIO_PULSER

No description provided by the author

LW_H2F_PIO_SC_CHECK_RFM0

No description provided by the author

LW_H2F_PIO_SC_CHECK_RFM1

No description provided by the author

LW_H2F_PIO_SC_CHECK_RFM2

No description provided by the author

LW_H2F_PIO_SC_CHECK_RFM3

No description provided by the author

LW_H2F_PIO_STATE_IN

No description provided by the author

LW_H2F_RAM_SC_RFM0

No description provided by the author

LW_H2F_RAM_SC_RFM1

No description provided by the author

LW_H2F_RAM_SC_RFM2

No description provided by the author

LW_H2F_RAM_SC_RFM3

No description provided by the author

LW_H2F_SPAN

enough.

NB_BITS_CFG_HR

No description provided by the author

NB_BYTES_CFG_HR

No description provided by the author

NB_HR

No description provided by the author

O_ALERT_0

No description provided by the author

O_ALERT_1

No description provided by the author

O_ALERT_2

No description provided by the author

O_ALERT_3

No description provided by the author

O_BBL_RST

No description provided by the author

O_CHIPSAT_0

No description provided by the author

O_CHIPSAT_1

No description provided by the author

O_CHIPSAT_2

No description provided by the author

O_CHIPSAT_3

No description provided by the author

O_CTEST

No description provided by the author

O_ENA_DCC_BUSY

No description provided by the author

O_ENA_DCC_RAMFULL

No description provided by the author

O_ENA_RFM0

No description provided by the author

O_ENA_RFM1

No description provided by the author

O_ENA_RFM2

No description provided by the author

O_ENA_RFM3

No description provided by the author

O_ENA_SCALERS

No description provided by the author

O_ENA_TRIG

No description provided by the author

O_FIFO_IN_VALID_0

No description provided by the author

O_FIFO_IN_VALID_1

No description provided by the author

O_FIFO_IN_VALID_2

No description provided by the author

O_FIFO_IN_VALID_3

No description provided by the author

O_HPS_BUSY

No description provided by the author

O_HR_END_RO_0

No description provided by the author

O_HR_END_RO_1

No description provided by the author

O_HR_END_RO_2

No description provided by the author

O_HR_END_RO_3

No description provided by the author

O_HR_TRANSMITON_0

masks for PIO_STATE_IN.

O_HR_TRANSMITON_1

No description provided by the author

O_HR_TRANSMITON_2

No description provided by the author

O_HR_TRANSMITON_3

No description provided by the author

O_ON_OFF_RFM0

No description provided by the author

O_ON_OFF_RFM1

No description provided by the author

O_ON_OFF_RFM2

No description provided by the author

O_ON_OFF_RFM3

No description provided by the author

O_PLL_LCK

No description provided by the author

O_RESET

masks for PIO_CTRL_OUT.

O_RESET_HR

No description provided by the author

O_RESET_SC

No description provided by the author

O_RST_SCALERS

No description provided by the author

O_SC_DONE_0

No description provided by the author

O_SC_DONE_1

No description provided by the author

O_SC_DONE_2

No description provided by the author

O_SC_DONE_3

No description provided by the author

O_SEL_CMD_SOURCE

No description provided by the author

O_SEL_TRIG_THRESH

No description provided by the author

O_SELECT_SC_RR

No description provided by the author

O_START_SC_0

No description provided by the author

O_START_SC_1

No description provided by the author

O_START_SC_2

No description provided by the author

O_START_SC_3

No description provided by the author

S_ACQ

No description provided by the author

S_FIFO_READY

No description provided by the author

S_IDLE

synchro states.

S_RAMFULL

No description provided by the author

S_RST_CNT24

No description provided by the author

S_RST_CNT48

No description provided by the author

S_START_RO

No description provided by the author

S_STOP_RUN

No description provided by the author

S_WAIT_END_RO

No description provided by the author

SHIFT_CMD_CODE

No description provided by the author

SHIFT_CMD_CODE_MEM

No description provided by the author

SHIFT_CMD_CODE_NOW

mask for sDCC command monitoring (via PIO_CNT24).

SHIFT_SYNCHRO_STATE

No description provided by the author