DQ-form, VSR register, register + offset operands */.

VX-form 2-register + ST + SIX operands */.

VX-form 1-register + SIM operands */.

VA-form 3-register + SHB operands */.

MD-form 2-register, 2 6-bit immediate operands */.

MDS-form 3-register, 1 6-bit immediate operands.

VX-form 2-register operands, r/none/r */.

the order is dest, a/s, b/imm for both arithmetic and logical operations.

X-form, 3-register operands + EH field */.

VA-form 4-register operands */.

VX-form 2-register + UIM operands */.

XX1-form 3-register operands, 1 VSR operand */.

XX2-form 3-register operands, 2 VSR operands */.

XX3-form 3 VSR operands */.

XX3-form 3 VSR operands + immediate */.

XX4-form, 4 VSR operands */.

Z23-form, 3-register operands + CY field */.

Determine if the build configuration requires a TOC pointer.

Generate MD-form opcode */.

Decrement CTR, and branch if CTR != 0.

Decrement CTR, and branch if CTR == 0.

not LT = G/E/U.

not GT = L/E/U.

not EQ = L/G/U.

aliases.

Branch if float not unordered (also branch on not summary overflow).

Branch if float unordered (also branch on summary overflow).

CMP with L=0 */.

64-bit pseudo operation */.

AFCFIW; AFCFIWCC */.

optional on 32-bit */.

more 64-bit operations */.

The final enumerated instruction value + 1.

The last instruction in this list.

Vector */.

VSX */.

* GENERAL: * * compiler allocates R3 up as temps * compiler allocates register variables R7-R27 * compiler allocates external registers R30 down * * compiler allocates register variables F17-F26 * compiler allocates external registers F26 down */.

branch unconditionally.

branch on cr value.

decrement ctr, branch on ctr != 0 and cr value.

decrement ctr, branch on ctr != 0.

branch on not cr value.

decrement ctr, branch on ctr == 0.

Any constant which fits into 32 bits.

Any constant which fits into 64 bits.

A symbolic memory location */.

Any argument */.

MMA accumulator register */.

2 result is zero.

1 result is positive.

0 result is negative.

3 summary overflow or FP compare w/ NaN.

A single bit of the CR register (0-31) */.

The condition registor (CR) */.

The count register */.

$n(REG) where n <= int64 */.

The fpscr register */.

Any fpr register */.

An even numbered fpr which can be used a fpr pair argument */.

A non-matched argument */.

$n(REG) where n <= int32 */.

A long offset argument to a branching instruction */.

Like C_LBRA, but requires an extra NOP for potential TOC restore by the linker.

An $n+reg memory arg where n is a 32 bit signed offset */.

The link register */.

must be the last */.

Any gpr register */.

An even numbered gpr which can be used a gpr pair argument */.

16 bit signed constant */.

Aliased names which may be generated by ppc64map for the optab.

34 bit signed constant */.

$n(REG) where n <= int16 */.

A short offset argument to a branching instruction */.

Aliased names which should be cleaned up, or integrated.

An $n+reg memory arg where n is a 16 bit signed offset */.

special processor register */.

An argument with Type obj.TYPE_TEXTSIZE */.

A thread local, initial-exec, type memory arg */.

A thread local, local-exec, type memory arg */.

15 bit unsigned constant */.

16 bit unsigned constant */.

1 bit unsigned constant */.

2 bit unsigned constant */.

3 bit unsigned constant */.

4 bit unsigned constant */.

5 bit unsigned constant */.

8 bit unsigned constant */.

Any vector register */.

Any vector-scalar register */.

An even numbered vsx register which can be used as a vsx register pair argument */.

An reg+reg memory arg */.

The constant zero */.

An $0+reg memory op */.

first external register */.

last register variable for 9g only */.

first register variable */.

mark flags */.

number of floating point registers */.

The preferred hardware nop instruction.

number of general registers */.

* powerpc 64 */.

* powerpc 64 */.

each rhs is OPVCC(_, _, _, _) */.

Offset is absolute.

Offset is relative to PC, RA should be 0.

A prefixed instruction crossing a 64B boundary.

MMA accumulator registers, these shadow VSR 0-31 e.g MMAx shadows VSRx*4-VSRx*4+3 or MMA0 shadows VSR0-VSR3.

CR bits.

An alias for a Condition Register bit 0.

Align FPR and VSR vectors such that when masked with 0x3F they produce an equivalent VSX register.

RBasePPC64 = 4096 */ R0=4096 ..

first of 1024 registers.

V0=4192 ..

VS0=4224 ..

-1 disables passing the first argument in register */.

context for closures */.

external registers allocated from here down */.

G */.

register variables allocated from here to REGMAX */.

reserved for runtime, duffzero and duffcopy */.

reserved for runtime, duffcopy */.

C ABI TLS base pointer */.

used by the linker */.

set to zero */.

OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture.

These are opcodes above which may generate different sequences depending on whether prefix opcode support is available.