DQ-form, VSR register, register + offset operands */.

VX-form 2-register + ST + SIX operands */.

VX-form 1-register + SIM operands */.

VA-form 3-register + SHB operands */.

VX-form 2-register operands, r/none/r */.

the order is dest, a/s, b/imm for both arithmetic and logical operations */.

X-form, 3-register operands + EH field */.

VA-form 4-register operands */.

VX-form 2-register + UIM operands */.

XX1-form 3-register operands, 1 VSR operand */.

XX2-form 3-register operands, 2 VSR operands */.

XX3-form 3 VSR operands */.

XX3-form 3 VSR operands + immediate */.

XX4-form, 4 VSR operands */.

Z23-form, 3-register operands + CY field */.

not LT = G/E/U.

not GT = L/E/U.

not EQ = L/G/U.

aliases.

Unordered-clear.

Unordered-set.

CMP with L=0 */.

64-bit pseudo operation */.

AFCFIW; AFCFIWCC */.

optional on 32-bit */.

more 64-bit operations */.

Vector */.

VSX */.

* GENERAL: * * compiler allocates R3 up as temps * compiler allocates register variables R7-R27 * compiler allocates external registers R30 down * * compiler allocates register variables F17-F26 * compiler allocates external registers F26 down */.

branch on cr value.

branch on ctr and cr value.

branch on ctr value.

value for likely.

branch on not cr value.

value for unlikely.

-0x8000 <= v < 0 */.

0 < v <= 0xFFFF */.

2 result is zero.

1 result is positive.

0 result is negative.

3 summary overflow or FP compare w/ NaN.

$n(REG) where int32 < n */.

other 64 (could subdivide further) */.

$n(REG) where int16 < n <= int32 */.

other 32 */.

must be the last */.

$n(REG) where n <= int16 */.

16 bit signed */.

register + signed offset.

special processor register */.

32 bit signed, low 16 bits 0 */.

conjecture: either (1) register + zeroed offset, or (2) "R0" implies zero or C_REG.

first external register */.

last register variable for 9g only */.

first register variable */.

mark flags */.

number of floating point registers */.

number of general registers */.

* powerpc 64 */.

* powerpc 64 */.

each rhs is OPVCC(_, _, _, _) */.

first of 1024 registers.

F0=4128 ..

RBasePPC64 = 4096 */ R0=4096 ..

first of 1024 registers.

V0=4160 ..

VS0=4192 ..

-1 disables passing the first argument in register */.

context for closures */.

external registers allocated from here down */.

G */.

register variables allocated from here to REGMAX */.

reserved for runtime, duffzero and duffcopy */.

reserved for runtime, duffcopy */.

C ABI TLS base pointer */.

used by the linker */.

set to zero */.

OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture.