package
0.0.0-20180601060148-d032931de3c3
Repository: https://github.com/cloudwise-opensource/gocrab.git
Documentation: pkg.go.dev

# README

cpuid

Package cpuid provides information about the CPU running the current program.

CPU features are detected on startup, and kept for fast access through the life of the application. Currently x86 / x64 (AMD64) is supported, and no external C (cgo) code is used, which should make the library very easy to use.

You can access the CPU information by accessing the shared CPU variable of the cpuid library.

Package home: https://github.com/klauspost/cpuid

GoDoc Build Status

features

CPU Instructions

  • CMOV (i686 CMOV)
  • NX (NX (No-Execute) bit)
  • AMD3DNOW (AMD 3DNOW)
  • AMD3DNOWEXT (AMD 3DNowExt)
  • MMX (standard MMX)
  • MMXEXT (SSE integer functions or AMD MMX ext)
  • SSE (SSE functions)
  • SSE2 (P4 SSE functions)
  • SSE3 (Prescott SSE3 functions)
  • SSSE3 (Conroe SSSE3 functions)
  • SSE4 (Penryn SSE4.1 functions)
  • SSE4A (AMD Barcelona microarchitecture SSE4a instructions)
  • SSE42 (Nehalem SSE4.2 functions)
  • AVX (AVX functions)
  • AVX2 (AVX2 functions)
  • FMA3 (Intel FMA 3)
  • FMA4 (Bulldozer FMA4 functions)
  • XOP (Bulldozer XOP functions)
  • F16C (Half-precision floating-point conversion)
  • BMI1 (Bit Manipulation Instruction Set 1)
  • BMI2 (Bit Manipulation Instruction Set 2)
  • TBM (AMD Trailing Bit Manipulation)
  • LZCNT (LZCNT instruction)
  • POPCNT (POPCNT instruction)
  • AESNI (Advanced Encryption Standard New Instructions)
  • CLMUL (Carry-less Multiplication)
  • HTT (Hyperthreading (enabled))
  • HLE (Hardware Lock Elision)
  • RTM (Restricted Transactional Memory)
  • RDRAND (RDRAND instruction is available)
  • RDSEED (RDSEED instruction is available)
  • ADX (Intel ADX (Multi-Precision Add-Carry Instruction Extensions))
  • SHA (Intel SHA Extensions)
  • AVX512F (AVX-512 Foundation)
  • AVX512DQ (AVX-512 Doubleword and Quadword Instructions)
  • AVX512IFMA (AVX-512 Integer Fused Multiply-Add Instructions)
  • AVX512PF (AVX-512 Prefetch Instructions)
  • AVX512ER (AVX-512 Exponential and Reciprocal Instructions)
  • AVX512CD (AVX-512 Conflict Detection Instructions)
  • AVX512BW (AVX-512 Byte and Word Instructions)
  • AVX512VL (AVX-512 Vector Length Extensions)
  • AVX512VBMI (AVX-512 Vector Bit Manipulation Instructions)
  • MPX (Intel MPX (Memory Protection Extensions))
  • ERMS (Enhanced REP MOVSB/STOSB)
  • RDTSCP (RDTSCP Instruction)
  • CX16 (CMPXCHG16B Instruction)
  • SGX (Software Guard Extensions, with activation details)

Performance

  • RDTSCP() Returns current cycle count. Can be used for benchmarking.
  • SSE2SLOW (SSE2 is supported, but usually not faster)
  • SSE3SLOW (SSE3 is supported, but usually not faster)
  • ATOM (Atom processor, some SSSE3 instructions are slower)
  • Cache line (Probable size of a cache line).
  • L1, L2, L3 Cache size on newer Intel/AMD CPUs.

Cpu Vendor/VM

  • Intel
  • AMD
  • VIA
  • Transmeta
  • NSC
  • KVM (Kernel-based Virtual Machine)
  • MSVM (Microsoft Hyper-V or Windows Virtual PC)
  • VMware
  • XenHVM

installing

go get github.com/klauspost/cpuid

example

package main

import (
	"fmt"
	"github.com/klauspost/cpuid"
)

func main() {
	// Print basic CPU information:
	fmt.Println("Name:", cpuid.CPU.BrandName)
	fmt.Println("PhysicalCores:", cpuid.CPU.PhysicalCores)
	fmt.Println("ThreadsPerCore:", cpuid.CPU.ThreadsPerCore)
	fmt.Println("LogicalCores:", cpuid.CPU.LogicalCores)
	fmt.Println("Family", cpuid.CPU.Family, "Model:", cpuid.CPU.Model)
	fmt.Println("Features:", cpuid.CPU.Features)
	fmt.Println("Cacheline bytes:", cpuid.CPU.CacheLine)
	fmt.Println("L1 Data Cache:", cpuid.CPU.Cache.L1D, "bytes")
	fmt.Println("L1 Instruction Cache:", cpuid.CPU.Cache.L1D, "bytes")
	fmt.Println("L2 Cache:", cpuid.CPU.Cache.L2, "bytes")
	fmt.Println("L3 Cache:", cpuid.CPU.Cache.L3, "bytes")

	// Test if we have a specific feature:
	if cpuid.CPU.SSE() {
		fmt.Println("We have Streaming SIMD Extensions")
	}
}

Sample output:

>go run main.go
Name: Intel(R) Core(TM) i5-2540M CPU @ 2.60GHz
PhysicalCores: 2
ThreadsPerCore: 2
LogicalCores: 4
Family 6 Model: 42
Features: CMOV,MMX,MMXEXT,SSE,SSE2,SSE3,SSSE3,SSE4.1,SSE4.2,AVX,AESNI,CLMUL
Cacheline bytes: 64
We have Streaming SIMD Extensions

private package

In the "private" folder you can find an autogenerated version of the library you can include in your own packages.

For this purpose all exports are removed, and functions and constants are lowercased.

This is not a recommended way of using the library, but provided for convenience, if it is difficult for you to use external packages.

license

This code is published under an MIT license. See LICENSE file for more information.

# Packages

No description provided by the author

# Functions

Detect will re-detect current CPU info.

# Constants

Intel ADX (Multi-Precision Add-Carry Instruction Extensions).
Advanced Encryption Standard New Instructions.
No description provided by the author
AMD 3DNOW.
AMD 3DNowExt.
Atom processor, some SSSE3 instructions are slower.
AVX functions.
AVX2 functions.
AVX-512 Byte and Word Instructions.
AVX-512 Conflict Detection Instructions.
AVX-512 Doubleword and Quadword Instructions.
AVX-512 Exponential and Reciprocal Instructions.
AVX-512 Foundation.
AVX-512 Integer Fused Multiply-Add Instructions.
AVX-512 Prefetch Instructions.
AVX-512 Vector Bit Manipulation Instructions.
AVX-512 Vector Length Extensions.
Bit Manipulation Instruction Set 1.
Bit Manipulation Instruction Set 2.
Carry-less Multiplication.
i686 CMOV.
CMPXCHG16B Instruction.
Enhanced REP MOVSB/STOSB.
Half-precision floating-point conversion.
Intel FMA 3.
Bulldozer FMA4 functions.
Hardware Lock Elision.
Hyperthreading (enabled).
No description provided by the author
Kernel-based Virtual Machine.
LZCNT instruction.
standard MMX.
SSE integer functions or AMD MMX ext.
Intel MPX (Memory Protection Extensions).
Microsoft Hyper-V or Windows Virtual PC.
No description provided by the author
NX (No-Execute) bit.
No description provided by the author
POPCNT instruction.
RDRAND instruction is available.
RDSEED instruction is available.
RDTSCP Instruction.
Restricted Transactional Memory.
Software Guard Extensions.
Intel SHA Extensions.
SSE functions.
P4 SSE functions.
SSE2 is supported, but usually not faster.
Prescott SSE3 functions.
SSE3 is supported, but usually not faster.
Penryn SSE4.1 functions.
Nehalem SSE4.2 functions.
AMD Barcelona microarchitecture SSE4a instructions.
Conroe SSSE3 functions.
AMD Trailing Bit Manipulation.
No description provided by the author
No description provided by the author
No description provided by the author
No description provided by the author
Bulldozer XOP functions.

# Variables

CPU contains information about the CPU as detected on startup, or when Detect last was called.

# Structs

CPUInfo contains information about the detected system CPU.
No description provided by the author

# Type aliases

Flags contains detected cpu features and caracteristics.
Vendor is a representation of a CPU vendor.