CPU Interpreter.

Decode opcode for debug messages.

Decode Two's Complement.

Initialization.

Memory Page Boundary cross detection.

Function used by readROM to avoid 'bytesread' return.

Read ROM and write it to the RAM.

Reset Vector // 0xFFFC | 0xFFFD (Little Endian).

Initialize TIA Variables.

xxxx xxx0 Color-Luminance Background.

xxxx xxx0 Color-Luminance Player 0.

xxxx xxx0 Color-Luminance Player 1.

xxxx xxx0 Color-Luminance Playfield.

00xx 0xxx Control Playfield, Ball, Collisions.

x000 0000 BL-PF -----.

---- ---- Clear Collision Latches.

xx00 0000 M0-PF M0-BL.

xx00 0000 Read Collision M0-P1 M0-P0.

xx00 0000 M1-PF M1-BL.

xx00 0000 M1-P0 M1-P1.

xx00 0000 P0-PF P0-BL.

xx00 0000 P1-PF P1-BL.

xx00 0000 P0-P1 M0-M1.

xxxx xxxx Graphics Register Player 0.

xxxx xxxx Graphics Register Player 1.

xxxx 0000 Horizontal Motion Ball.

---- ---- Clear Horizontal Move Registers.

xxxx 0000 Horizontal Motion Missle 0.

xxxx 0000 Horizontal Motion Missle 1.

---- ---- Apply Horizontal Motion.

xxxx 0000 Horizontal Motion Player 0.

xxxx 0000 Horizontal Motion Player 1.

x000 0000 Read Pot Port 0.

x000 0000 Read Pot Port 1.

x000 0000 Read Pot Port 2.

x000 0000 Read Pot Port 3.

x000 0000 Read Input (Trigger) 0.

x000 0000 Read Input (Trigger) 1.

Timer output.

00xx 0xxx Number-Size player/missle 0.

00xx 0xxx Number-Size player/missle 1.

xxxx 0000 Playfield Register Byte 0.

xxxx 0000 Playfield Register Byte 1.

xxxx 0000 Playfield Register Byte 2.

0000 x000 Reflection Player 0.

0000 x000 Reflection Player 1.

---- ---- Reset Player 0.

---- ---- Reset Player 1.

---- ---- Reset Horizontal Sync Counter.

Port A data register for joysticks: Bits 4-7 for player 1.

Port B data (console switches).

Set 1024 clock interval.

Set 1 clock interval.

Set 64 clock interval.

Set 8 clock interval.

Timer interrupt flag, which is 0 if the timer hasn't passed 0 yet, and is set to 128 (bit 7 on).

xx00 00x0 Vertical Blank Set-Clear.

0000 00x0 Vertical Sync Set-Clear.

---- ---- Wait for Horizontal Blank.

Accumulator.

// 16 pins of processor that points to memory for read or write operations.

Cycles per second.

Enable or disable CPU during WSYNC.

0 for 6507, 1 for 6502 CPU interpreter.

Cycles counter.

Debug.

Instructions per second.

Memory.

RIOT Write Addresses and its mirrors.

TIA Read-Only additional Registers (0x30 - 0x3D), requested as READ addresses 0x00 - 0x13.

Easily detect when CPU finished running the cycles of an opcode.

Number of bytes from an opcode.

Opcode cycle counter.

Opcode extra cycle.

Number of cycles from an opcode.

The stack pointer is addressing 256 bytes in page 1 of memory, ie.

Pause.

Program Counter.

Program Counter passed as CLI Argument (temp value).

Stack Pointer.

Tells Graphics that a TIA register was changed (values >= 0 (addresses) will be detected).

Index Register X.

-------------------- Players Vertical Positioning -------------------- //.

Index Register Y.

Fullscreen / Video Modes.